[PATCH v3 5/5] arm64: dts: rockchip: Add HDMI0 PHY PLL clock source to VOP2 on RK3588

[Cristian Ciocaltea]

VOP2 on RK3588 is able to use the HDMI PHY PLL as an alternative and
more accurate pixel clock source to improve handling of display modes up
to 4K@60Hz on video ports 0, 1 and 2.

For now only HDMI0 output is supported, hence add the related PLL clock.

Tested-by: FUKAUMI Naoki <na...@radxa.com>
Signed-off-by: Cristian Ciocaltea <cristian.ciocal...@collabora.com>
---
 arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi 
b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
index 
c2d1f08e55d4cb4b4d2b6a89f26542fdc99fd604..13146793188c466faabe6a88e6230ba09f36770c
 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -1261,14 +1261,16 @@ vop: vop@fdd90000 {
                         <&cru DCLK_VOP1>,
                         <&cru DCLK_VOP2>,
                         <&cru DCLK_VOP3>,
-                        <&cru PCLK_VOP_ROOT>;
+                        <&cru PCLK_VOP_ROOT>,
+                        <&hdptxphy_hdmi0>;
                clock-names = "aclk",
                              "hclk",
                              "dclk_vp0",
                              "dclk_vp1",
                              "dclk_vp2",
                              "dclk_vp3",
-                             "pclk_vop";
+                             "pclk_vop",
+                             "pll_hdmiphy0";
                iommus = <&vop_mmu>;
                power-domains = <&power RK3588_PD_VOP>;
                rockchip,grf = <&sys_grf>;

-- 
2.48.1