Add support for the eDP0 output on RK3588 SoC.
Signed-off-by: Damon Ding <damon.d...@rock-chips.com>
---
Changes in v3:
- Remove currently unsupported property '#sound-dai-cells'
Changes in v4:
- Remove currently unsupported clock 'spdif'
---
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 28 +++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
index 7e125897b0cd..7ab460c28c51 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -1411,6 +1411,34 @@ hdmi0_out: port@1 {
};
};
+ edp0: edp@fdec0000 {
+ compatible = "rockchip,rk3588-edp";
+ reg = <0x0 0xfdec0000 0x0 0x1000>;
+ clocks = <&cru CLK_EDP0_24M>, <&cru PCLK_EDP0>;
+ clock-names = "dp", "pclk";
+ interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>;
+ phys = <&hdptxphy0>;
+ phy-names = "dp";
+ power-domains = <&power RK3588_PD_VO1>;
+ resets = <&cru SRST_EDP0_24M>, <&cru SRST_P_EDP0>;
+ reset-names = "dp", "apb";
+ rockchip,grf = <&vo1_grf>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ edp0_in: port@0 {
+ reg = <0>;
+ };
+
+ edp0_out: port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
qos_gpu_m0: qos@fdf35000 {
compatible = "rockchip,rk3588-qos", "syscon";
reg = <0x0 0xfdf35000 0x0 0x20>;
--
2.34.1
