On Thu, Dec 19, 2024 at 11:33:59PM +0200, Jani Nikula wrote:
> Write the payload allocation table for 128b/132b SST. Use VCPID 1 and
> start from slot 0, with dp_m_n.tu slots.
>
> This is preparation for enabling 128b/132b SST. This path is not
> reachable yet. Indeed, we don't yet compute TU for 128b/132b SST.
>
> Signed-off-by: Jani Nikula <jani.nik...@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 6f813bf85b23..64528ff8856e 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2669,6 +2669,12 @@ static void mtl_ddi_pre_enable_dp(struct
> intel_atomic_state *state,
> /* 6.o Configure and enable FEC if needed */
> intel_ddi_enable_fec(encoder, crtc_state);
>
> + /* 7.a 128b/132b SST. */
> + if (!is_mst && intel_dp_is_uhbr(crtc_state)) {
> + /* VCPID 1, start slot 0 for 128b/132b, tu slots */
> + drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0,
> crtc_state->dp_m_n.tu);
I would handle the error by sending a modeset retry uevent. Either way:
Reviewed-by: Imre Deak <imre.d...@intel.com>
> + }
> +
> if (!is_mst)
> intel_dsc_dp_pps_write(encoder, crtc_state);
> }
> @@ -2808,6 +2814,11 @@ static void tgl_ddi_pre_enable_dp(struct
> intel_atomic_state *state,
> /* 7.l Configure and enable FEC if needed */
> intel_ddi_enable_fec(encoder, crtc_state);
>
> + if (!is_mst && intel_dp_is_uhbr(crtc_state)) {
> + /* VCPID 1, start slot 0 for 128b/132b, tu slots */
> + drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0,
> crtc_state->dp_m_n.tu);
> + }
> +
> if (!is_mst)
> intel_dsc_dp_pps_write(encoder, crtc_state);
> }
> --
> 2.39.5
>
