From: Andy Yan <andy....@rock-chips.com>

Add VOP and VOP_MMU found on rk3576.

Signed-off-by: Andy Yan <andy....@rock-chips.com>
---

(no changes since v1)

 arch/arm64/boot/dts/rockchip/rk3576.dtsi | 68 ++++++++++++++++++++++++
 1 file changed, 68 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi 
b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
index 436232ffe4d1..130d11a2cc89 100644
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
@@ -393,6 +393,11 @@ opp-950000000 {
                };
        };
 
+       display_subsystem: display-subsystem {
+               compatible = "rockchip,display-subsystem";
+               ports = <&vop_out>;
+       };
+
        firmware {
                scmi: scmi {
                        compatible = "arm,scmi-smc";
@@ -826,6 +831,69 @@ gpu: gpu@27800000 {
                        status = "disabled";
                };
 
+               vop: vop@27d00000 {
+                       compatible = "rockchip,rk3576-vop";
+                       reg = <0x0 0x27d00000 0x0 0x3000>, <0x0 0x27d05000 0x0 
0x1000>;
+                       reg-names = "vop", "gamma-lut";
+                       interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "vop-sys",
+                                         "vop-vp0",
+                                         "vop-vp1",
+                                         "vop-vp2";
+                       clocks = <&cru ACLK_VOP>,
+                                <&cru HCLK_VOP>,
+                                <&cru DCLK_VP0>,
+                                <&cru DCLK_VP1>,
+                                <&cru DCLK_VP2>;
+                       clock-names = "aclk",
+                                     "hclk",
+                                     "dclk_vp0",
+                                     "dclk_vp1",
+                                     "dclk_vp2";
+                       iommus = <&vop_mmu>;
+                       power-domains = <&power RK3576_PD_VOP>;
+                       rockchip,grf = <&sys_grf>;
+                       rockchip,pmu = <&pmu>;
+                       status = "disabled";
+
+                       vop_out: ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               vp0: port@0 {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+                                       reg = <0>;
+                               };
+
+                               vp1: port@1 {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+                                       reg = <1>;
+                               };
+
+                               vp2: port@2 {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+                                       reg = <2>;
+                               };
+                       };
+               };
+
+               vop_mmu: iommu@27d07e00 {
+                       compatible = "rockchip,rk3576-iommu", 
"rockchip,rk3568-iommu";
+                       reg = <0x0 0x27d07e00 0x0 0x100>, <0x0 0x27d07f00 0x0 
0x100>;
+                       interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
+                       clock-names = "aclk", "iface";
+                       #iommu-cells = <0>;
+                       power-domains = <&power RK3576_PD_VOP>;
+                       status = "disabled";
+               };
+
                qos_hdcp1: qos@27f02000 {
                        compatible = "rockchip,rk3576-qos", "syscon";
                        reg = <0x0 0x27f02000 0x0 0x20>;
-- 
2.34.1

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