From: Konrad Dybcio <konrad.dyb...@oss.qualcomm.com> Add a register that contains the GMU core firmware version on non- legacy (non-sdm845-family) SoCs.
The name is guesstimated based on what it does downstream, but it'll do. Signed-off-by: Konrad Dybcio <konrad.dyb...@oss.qualcomm.com> --- drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml b/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml index 6531749d30f4e4e57ca4f7b43a28b7829504a9f3..3d2cc339b8f19c8d24b2c9144569b2364afc5ebc 100644 --- a/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml +++ b/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml @@ -52,6 +52,11 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> <reg32 offset="0x23fd" name="GMU_DCVS_PERF_SETTING"/> <reg32 offset="0x23fe" name="GMU_DCVS_BW_SETTING"/> <reg32 offset="0x23ff" name="GMU_DCVS_RETURN"/> + <reg32 offset="0x2bf8" name="GMU_CORE_FW_VERSION"> + <bitfield name="MAJOR" low="28" high="31"/> + <bitfield name="MINOR" low="16" high="27"/> + <bitfield name="STEP" low="0" high="15"/> + </reg32> <reg32 offset="0x4c00" name="GMU_ICACHE_CONFIG"/> <reg32 offset="0x4c01" name="GMU_DCACHE_CONFIG"/> <reg32 offset="0x4c0f" name="GMU_SYS_BUS_CONFIG"/> -- 2.47.1
