Hi Heiko,
On 2024/12/18 20:45, Heiko Stübner wrote:
Hi Damon,
Am Montag, 16. Dezember 2024, 04:12:25 CET schrieb Damon Ding:
The related nodes are hdptxphy1_grf, hdptxphy1 and edp1. And the
aliases edp0 and edp1 are added to separate two independent eDP
devices.
Signed-off-by: Damon Ding <damon.d...@rock-chips.com>
---
.../arm64/boot/dts/rockchip/rk3588-extra.dtsi | 55 +++++++++++++++++++
1 file changed, 55 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
index 0ce0934ec6b7..17cc0b619744 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
@@ -7,6 +7,11 @@
#include "rk3588-extra-pinctrl.dtsi"
/ {
+ aliases {
+ edp0 = &edp0;
+ edp1 = &edp1;
+ };
+
drop aliases please
I will drop it and use the registers to separate edp0 and edp1 in the
next version.
@@ -67,6 +72,11 @@ u2phy1_otg: otg-port {
};
};
+ hdptxphy1_grf: syscon@fd5e4000 {
+ compatible = "rockchip,rk3588-hdptxphy-grf", "syscon";
+ reg = <0x0 0xfd5e4000 0x0 0x100>;
+ };
+
i2s8_8ch: i2s@fddc8000 {
compatible = "rockchip,rk3588-i2s-tdm";
reg = <0x0 0xfddc8000 0x0 0x1000>;
@@ -395,6 +434,22 @@ sata-port@0 {
};
};
+ hdptxphy1: phy@fed70000 {
+ compatible = "rockchip,rk3588-hdptx-phy";
+ reg = <0x0 0xfed70000 0x0 0x2000>;
+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX1>;
+ clock-names = "ref", "apb";
+ #phy-cells = <0>;
+ resets = <&cru SRST_HDPTX1>, <&cru SRST_P_HDPTX1>,
+ <&cru SRST_HDPTX1_INIT>, <&cru SRST_HDPTX1_CMN>,
+ <&cru SRST_HDPTX1_LANE>, <&cru SRST_HDPTX1_ROPLL>,
+ <&cru SRST_HDPTX1_LCPLL>;
+ reset-names = "phy", "apb", "init", "cmn", "lane", "ropll",
+ "lcpll";
+ rockchip,grf = <&hdptxphy1_grf>;
+ status = "disabled";
+ };
the hdptxphy nodes should be their own patch, also because most likely
Cristian's patch for hdmi1 [0] will be slightly faster.
Indeed, it is good to add edp1 node only.
[0]
https://lore.kernel.org/r/20241211-rk3588-hdmi1-v2-2-02cdca22f...@collabora.com
Best regards,
Damon
