[PATCH v4 7/7] drm/rcar-du: Add support for r8a779h0

[Tomi Valkeinen]

From: Tomi Valkeinen <tomi.valkeinen+rene...@ideasonboard.com>

Add support for r8a779h0. It is very similar to r8a779g0, but has only
one output.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen+rene...@ideasonboard.com>
Tested-by: Geert Uytterhoeven <geert+rene...@glider.be>
Reviewed-by: Laurent Pinchart <laurent.pinchart+rene...@ideasonboard.com>
---
 drivers/gpu/drm/renesas/rcar-du/rcar_du_drv.c   | 18 ++++++++++++++++++
 drivers/gpu/drm/renesas/rcar-du/rcar_du_group.c |  4 +++-
 2 files changed, 21 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_du_drv.c 
b/drivers/gpu/drm/renesas/rcar-du/rcar_du_drv.c
index fb719d9aff10..7858e10839f2 100644
--- a/drivers/gpu/drm/renesas/rcar-du/rcar_du_drv.c
+++ b/drivers/gpu/drm/renesas/rcar-du/rcar_du_drv.c
@@ -545,6 +545,23 @@ static const struct rcar_du_device_info 
rcar_du_r8a779g0_info = {
        .dsi_clk_mask =  BIT(1) | BIT(0),
 };
 
+static const struct rcar_du_device_info rcar_du_r8a779h0_info = {
+       .gen = 4,
+       .features = RCAR_DU_FEATURE_CRTC_IRQ
+                 | RCAR_DU_FEATURE_VSP1_SOURCE
+                 | RCAR_DU_FEATURE_NO_BLENDING,
+       .channels_mask = BIT(0),
+       .routes = {
+               /* R8A779H0 has one MIPI DSI output. */
+               [RCAR_DU_OUTPUT_DSI0] = {
+                       .possible_crtcs = BIT(0),
+                       .port = 0,
+               },
+       },
+       .num_rpf = 5,
+       .dsi_clk_mask = BIT(0),
+};
+
 static const struct of_device_id rcar_du_of_table[] = {
        { .compatible = "renesas,du-r8a7742", .data = &rcar_du_r8a7790_info },
        { .compatible = "renesas,du-r8a7743", .data = &rzg1_du_r8a7743_info },
@@ -571,6 +588,7 @@ static const struct of_device_id rcar_du_of_table[] = {
        { .compatible = "renesas,du-r8a77995", .data = &rcar_du_r8a7799x_info },
        { .compatible = "renesas,du-r8a779a0", .data = &rcar_du_r8a779a0_info },
        { .compatible = "renesas,du-r8a779g0", .data = &rcar_du_r8a779g0_info },
+       { .compatible = "renesas,du-r8a779h0", .data = &rcar_du_r8a779h0_info },
        { }
 };
 
diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_du_group.c 
b/drivers/gpu/drm/renesas/rcar-du/rcar_du_group.c
index 1ec806c8e013..068c106e586c 100644
--- a/drivers/gpu/drm/renesas/rcar-du/rcar_du_group.c
+++ b/drivers/gpu/drm/renesas/rcar-du/rcar_du_group.c
@@ -107,10 +107,12 @@ static void rcar_du_group_setup_didsr(struct 
rcar_du_group *rgrp)
                 */
                rcrtc = rcdu->crtcs;
                num_crtcs = rcdu->num_crtcs;
-       } else if (rcdu->info->gen >= 3 && rgrp->num_crtcs > 1) {
+       } else if ((rcdu->info->gen == 3 && rgrp->num_crtcs > 1) ||
+                  rcdu->info->gen == 4) {
                /*
                 * On Gen3 dot clocks are setup through per-group registers,
                 * only available when the group has two channels.
+                * On Gen4 the registers are there for single channel too.
                 */
                rcrtc = &rcdu->crtcs[rgrp->index * 2];
                num_crtcs = rgrp->num_crtcs;

-- 
2.43.0