From: Dominik Grzegorzek <dominik.grzegor...@intel.com>
In order to turn on debug capabilities, (i.e. breakpoints), TD_CTL
and some other registers needs to be programmed. Implement eudebug
mode enabling including eudebug related workarounds.
v2: Move workarounds to xe_wa_oob. Use reg_sr directly instead of
xe_rtp as it suits better for dynamic manipulation of those register we
do later in the series.
v3: get rid of undefining XE_MCR_REG (Mika)
Signed-off-by: Dominik Grzegorzek <dominik.grzegor...@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuopp...@linux.intel.com>
---
drivers/gpu/drm/xe/regs/xe_engine_regs.h | 4 ++
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 10 +++++
drivers/gpu/drm/xe/xe_eudebug.c | 49 ++++++++++++++++++++++++
drivers/gpu/drm/xe/xe_eudebug.h | 3 ++
drivers/gpu/drm/xe/xe_hw_engine.c | 2 +
drivers/gpu/drm/xe/xe_wa_oob.rules | 2 +
6 files changed, 70 insertions(+)
diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
index 7c78496e6213..e45c4d5378e5 100644
--- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
@@ -115,6 +115,10 @@
#define INDIRECT_RING_STATE(base) XE_REG((base) + 0x108)
+#define CS_DEBUG_MODE2(base) XE_REG((base) + 0xd8,
XE_REG_OPTION_MASKED)
+#define INST_STATE_CACHE_INVALIDATE REG_BIT(6)
+#define GLOBAL_DEBUG_ENABLE REG_BIT(5)
+
#define RING_BBADDR(base) XE_REG((base) + 0x140)
#define RING_BBADDR_UDW(base) XE_REG((base) + 0x168)
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 162f18e975da..cd8c49a9000f 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -455,6 +455,14 @@
#define DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA REG_BIT(15)
#define CLEAR_OPTIMIZATION_DISABLE REG_BIT(6)
+#define TD_CTL XE_REG_MCR(0xe400)
+#define TD_CTL_FEH_AND_FEE_ENABLE REG_BIT(7) /* forced halt and
exception */
+#define TD_CTL_FORCE_EXTERNAL_HALT REG_BIT(6)
+#define TD_CTL_FORCE_THREAD_BREAKPOINT_ENABLE REG_BIT(4)
+#define TD_CTL_FORCE_EXCEPTION REG_BIT(3)
+#define TD_CTL_BREAKPOINT_ENABLE REG_BIT(2)
+#define TD_CTL_GLOBAL_DEBUG_ENABLE REG_BIT(0) /* XeHP */
+
#define CACHE_MODE_SS XE_REG_MCR(0xe420,
XE_REG_OPTION_MASKED)
#define DISABLE_ECC REG_BIT(5)
#define ENABLE_PREFETCH_INTO_IC REG_BIT(3)
@@ -481,11 +489,13 @@
#define MDQ_ARBITRATION_MODE REG_BIT(12)
#define STALL_DOP_GATING_DISABLE REG_BIT(5)
#define EARLY_EOT_DIS REG_BIT(1)
+#define STALL_DOP_GATING_DISABLE REG_BIT(5)
#define ROW_CHICKEN2 XE_REG_MCR(0xe4f4,
XE_REG_OPTION_MASKED)
#define DISABLE_READ_SUPPRESSION REG_BIT(15)
#define DISABLE_EARLY_READ REG_BIT(14)
#define ENABLE_LARGE_GRF_MODE REG_BIT(12)
+#define XEHPC_DISABLE_BTB REG_BIT(11)
#define PUSH_CONST_DEREF_HOLD_DIS REG_BIT(8)
#define DISABLE_TDL_SVHS_GATING REG_BIT(1)
#define DISABLE_DOP_GATING REG_BIT(0)
diff --git a/drivers/gpu/drm/xe/xe_eudebug.c b/drivers/gpu/drm/xe/xe_eudebug.c
index cbcf7a72fdba..fecb7c8a9779 100644
--- a/drivers/gpu/drm/xe/xe_eudebug.c
+++ b/drivers/gpu/drm/xe/xe_eudebug.c
@@ -10,13 +10,21 @@
#include <drm/drm_managed.h>
+#include <generated/xe_wa_oob.h>
+
+#include "regs/xe_gt_regs.h"
+#include "regs/xe_engine_regs.h"
+
#include "xe_assert.h"
#include "xe_device.h"
#include "xe_eudebug.h"
#include "xe_eudebug_types.h"
#include "xe_exec_queue.h"
#include "xe_macros.h"
+#include "xe_reg_sr.h"
+#include "xe_rtp.h"
#include "xe_vm.h"
+#include "xe_wa.h"
/*
* If there is no detected event read by userspace, during this period, assume
@@ -947,6 +955,47 @@ int xe_eudebug_connect_ioctl(struct drm_device *dev,
return ret;
}
+static void add_sr_entry(struct xe_hw_engine *hwe,
+ struct xe_reg_mcr mcr_reg,
+ u32 mask)
+{
+ const struct xe_reg_sr_entry sr_entry = {
+ .reg = mcr_reg.__reg,
+ .clr_bits = mask,
+ .set_bits = mask,
+ .read_mask = mask,
+ };
+
+ xe_reg_sr_add(&hwe->reg_sr, &sr_entry, hwe->gt);
+}
+
+void xe_eudebug_init_hw_engine(struct xe_hw_engine *hwe)
+{
+ struct xe_gt *gt = hwe->gt;
+ struct xe_device *xe = gt_to_xe(gt);
+
+ if (!xe->eudebug.available)
+ return;
+
+ if (!xe_rtp_match_first_render_or_compute(gt, hwe))
+ return;
+
+ if (XE_WA(gt, 18022722726))
+ add_sr_entry(hwe, ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
+
+ if (XE_WA(gt, 14015474168))
+ add_sr_entry(hwe, ROW_CHICKEN2, XEHPC_DISABLE_BTB);
+
+ if (xe->info.graphics_verx100 >= 1200)
+ add_sr_entry(hwe, TD_CTL,
+ TD_CTL_BREAKPOINT_ENABLE |
+ TD_CTL_FORCE_THREAD_BREAKPOINT_ENABLE |
+ TD_CTL_FEH_AND_FEE_ENABLE);
+
+ if (xe->info.graphics_verx100 >= 1250)
+ add_sr_entry(hwe, TD_CTL, TD_CTL_GLOBAL_DEBUG_ENABLE);
+}
+
void xe_eudebug_init(struct xe_device *xe)
{
spin_lock_init(&xe->eudebug.lock);
diff --git a/drivers/gpu/drm/xe/xe_eudebug.h b/drivers/gpu/drm/xe/xe_eudebug.h
index 326ddbd50651..3cd6bc7bb682 100644
--- a/drivers/gpu/drm/xe/xe_eudebug.h
+++ b/drivers/gpu/drm/xe/xe_eudebug.h
@@ -11,6 +11,7 @@ struct xe_device;
struct xe_file;
struct xe_vm;
struct xe_exec_queue;
+struct xe_hw_engine;
#if IS_ENABLED(CONFIG_DRM_XE_EUDEBUG)
@@ -20,6 +21,7 @@ int xe_eudebug_connect_ioctl(struct drm_device *dev,
void xe_eudebug_init(struct xe_device *xe);
void xe_eudebug_fini(struct xe_device *xe);
+void xe_eudebug_init_hw_engine(struct xe_hw_engine *hwe);
void xe_eudebug_file_open(struct xe_file *xef);
void xe_eudebug_file_close(struct xe_file *xef);
@@ -38,6 +40,7 @@ static inline int xe_eudebug_connect_ioctl(struct drm_device
*dev,
static inline void xe_eudebug_init(struct xe_device *xe) { }
static inline void xe_eudebug_fini(struct xe_device *xe) { }
+static inline void xe_eudebug_init_hw_engine(struct xe_hw_engine *hwe) { }
static inline void xe_eudebug_file_open(struct xe_file *xef) { }
static inline void xe_eudebug_file_close(struct xe_file *xef) { }
diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c
b/drivers/gpu/drm/xe/xe_hw_engine.c
index c4b0dc3be39c..8a188ddc99f4 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -16,6 +16,7 @@
#include "xe_assert.h"
#include "xe_bo.h"
#include "xe_device.h"
+#include "xe_eudebug.h"
#include "xe_execlist.h"
#include "xe_force_wake.h"
#include "xe_gsc.h"
@@ -558,6 +559,7 @@ static void hw_engine_init_early(struct xe_gt *gt, struct
xe_hw_engine *hwe,
xe_tuning_process_engine(hwe);
xe_wa_process_engine(hwe);
hw_engine_setup_default_state(hwe);
+ xe_eudebug_init_hw_engine(hwe);
xe_reg_sr_init(&hwe->reg_whitelist, hwe->name, gt_to_xe(gt));
xe_reg_whitelist_process_engine(hwe);
diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules
b/drivers/gpu/drm/xe/xe_wa_oob.rules
index 3ed12a85cc60..cc2f28663072 100644
--- a/drivers/gpu/drm/xe/xe_wa_oob.rules
+++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
@@ -42,3 +42,5 @@
no_media_l3 MEDIA_VERSION(3000)
14022866841 GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0)
MEDIA_VERSION(3000), MEDIA_STEP(A0, B0)
+18022722726 GRAPHICS_VERSION_RANGE(1250, 1274)
+14015474168 PLATFORM(PVC)
--
2.43.0
