On Tue, Nov 12, 2024 at 06:05:41PM +0800, Liu Ying wrote: > The LVDS panel "multi-inno,mi1010ait-1cp" used on this platform has > a typical pixel clock rate of 70MHz. Set "media_disp2_pix" clock rate > to that rate, instead of the original 68.9MHz. The LVDS serial clock > is controlled by "media_ldb" clock. It should run at 490MHz(7-fold the > pixel clock rate due to single LVDS link). Set "video_pll1" clock rate > and "media_ldb" to 490MHz to achieve that. > > This should be able to suppress this LDB driver warning: > [ 17.206644] fsl-ldb 32ec0000.blk-ctrl:bridge@5c: Configured LDB clock > (70000000 Hz) does not match requested LVDS clock: 490000000 Hz > > This also makes the display mode used by the panel pass mode validation > against pixel clock rate and "media_ldb" clock rate in a certain display > driver. > > Signed-off-by: Liu Ying <victor....@nxp.com>
Applied, thanks!
