On 26.11.2024 3:06 PM, Akhil P Oommen wrote:
> From: Jie Zhang <quic_ji...@quicinc.com>
>
> Add gpu and gmu nodes for qcs615 chipset.
>
> Signed-off-by: Jie Zhang <quic_ji...@quicinc.com>
> Signed-off-by: Akhil P Oommen <quic_akhi...@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/qcs615.dtsi | 86
> ++++++++++++++++++++++++++++++++++++
> 1 file changed, 86 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi
> b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> index
> 8df26efde3fd6c0f85b9bcddb461fae33687dc75..f6a3fbbda962f01d6cf2d5c156ea1d1d846f310a
> 100644
> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> @@ -387,6 +387,11 @@ smem_region: smem@86000000 {
> no-map;
> hwlocks = <&tcsr_mutex 3>;
> };
> +
> + pil_gpu_mem: pil-gpu@97715000 {
> + reg = <0x0 0x97715000 0x0 0x2000>;
> + no-map;
> + };
> };
>
> soc: soc@0 {
> @@ -508,6 +513,87 @@ qup_uart0_rx: qup-uart0-rx-state {
> };
> };
>
> + gpu: gpu@5000000 {
> + compatible = "qcom,adreno-612.0", "qcom,adreno";
> + reg = <0x0 0x05000000 0x0 0x90000>;
> + reg-names = "kgsl_3d0_reg_memory";
> +
> + clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>,
> + <&gcc GCC_DDRSS_GPU_AXI_CLK>,
> + <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
> + <&gpucc GPU_CC_CX_GMU_CLK>,
> + <&gpucc GPU_CC_CXO_CLK>,
> + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
This one belongs under the adreno_smmu node
Konrad
