[PATCH v3 3/7] drm/msm: adreno: dynamically generate GMU bw table

[Neil Armstrong]

The Adreno GPU Management Unit (GMU) can also scale the ddr
bandwidth along the frequency and power domain level, but for
now we statically fill the bw_table with values from the
downstream driver.

Only the first entry is used, which is a disable vote, so we
currently rely on scaling via the linux interconnect paths.

Let's dynamically generate the bw_table with the vote values
previously calculated from the OPPs.

Those entried will then be used by the GMU when passing the
appropriate bandwidth level while voting for a gpu frequency.

Signed-off-by: Neil Armstrong <neil.armstr...@linaro.org>
---
 drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 39 ++++++++++++++++++++++++++++++++---
 1 file changed, 36 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c 
b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
index 
cb8844ed46b29c4569d05eb7a24f7b27e173190f..fe1946650425b749bad483dad1e630bc8be83abc
 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
@@ -621,6 +621,35 @@ static void a740_build_bw_table(struct 
a6xx_hfi_msg_bw_table *msg)
        msg->cnoc_cmds_data[1][0] = 0x60000001;
 }
 
+static void a740_generate_bw_table(const struct a6xx_info *info, struct 
a6xx_gmu *gmu,
+                                  struct a6xx_hfi_msg_bw_table *msg)
+{
+       unsigned int i, j;
+
+       msg->ddr_wait_bitmask = 0x7;
+
+       for (i = 0; i < GMU_MAX_BCMS; i++) {
+               if (!info->bcms[i].name)
+                       break;
+               msg->ddr_cmds_addrs[i] = cmd_db_read_addr(info->bcms[i].name);
+       }
+       msg->ddr_cmds_num = i;
+
+       for (i = 0; i < gmu->nr_gpu_bws; ++i)
+               for (j = 0; j < msg->ddr_cmds_num; j++)
+                       msg->ddr_cmds_data[i][j] = gmu->gpu_ib_votes[i][j];
+       msg->bw_level_num = gmu->nr_gpu_bws;
+
+       /* TODO also generate CNOC commands */
+
+       msg->cnoc_cmds_num = 1;
+       msg->cnoc_wait_bitmask = 0x1;
+
+       msg->cnoc_cmds_addrs[0] = cmd_db_read_addr("CN0");
+       msg->cnoc_cmds_data[0][0] = 0x40000000;
+       msg->cnoc_cmds_data[1][0] = 0x60000001;
+}
+
 static void a6xx_build_bw_table(struct a6xx_hfi_msg_bw_table *msg)
 {
        /* Send a single "off" entry since the 630 GMU doesn't do bus scaling */
@@ -664,6 +693,7 @@ static int a6xx_hfi_send_bw_table(struct a6xx_gmu *gmu)
        struct a6xx_hfi_msg_bw_table *msg;
        struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
        struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
+       const struct a6xx_info *info = adreno_gpu->info->a6xx;
 
        if (gmu->bw_table)
                goto send;
@@ -690,9 +720,12 @@ static int a6xx_hfi_send_bw_table(struct a6xx_gmu *gmu)
                a690_build_bw_table(msg);
        else if (adreno_is_a730(adreno_gpu))
                a730_build_bw_table(msg);
-       else if (adreno_is_a740_family(adreno_gpu))
-               a740_build_bw_table(msg);
-       else
+       else if (adreno_is_a740_family(adreno_gpu)) {
+               if (info->bcms && gmu->nr_gpu_bws > 1)
+                       a740_generate_bw_table(info, gmu, msg);
+               else
+                       a740_build_bw_table(msg);
+       } else
                a6xx_build_bw_table(msg);
 
        gmu->bw_table = msg;

-- 
2.34.1