Make spelling and punctuation changes to ease reading of the comments.

Signed-off-by: Randy Dunlap <rdun...@infradead.org>
Cc: Alex Deucher <alexander.deuc...@amd.com>
Cc: Christian König <christian.koe...@amd.com>
Cc: Xinhui Pan <xinhui....@amd.com>
Cc: amd-...@lists.freedesktop.org
Cc: David Airlie <airl...@gmail.com>
Cc: Simona Vetter <sim...@ffwll.ch>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |   30 +++++++++----------
 1 file changed, 15 insertions(+), 15 deletions(-)

--- linux-next-20241125.orig/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ linux-next-20241125/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -204,9 +204,9 @@ static inline void amdgpu_device_stop_pe
  * DOC: pcie_replay_count
  *
  * The amdgpu driver provides a sysfs API for reporting the total number
- * of PCIe replays (NAKs)
+ * of PCIe replays (NAKs).
  * The file pcie_replay_count is used for this and returns the total
- * number of replays as a sum of the NAKs generated and NAKs received
+ * number of replays as a sum of the NAKs generated and NAKs received.
  */
 
 static ssize_t amdgpu_device_get_pcie_replay_count(struct device *dev,
@@ -429,8 +429,8 @@ bool amdgpu_device_supports_boco(struct
  * @dev: drm_device pointer
  *
  * Return:
- * 1 if the device supporte BACO;
- * 3 if the device support MACO (only works if BACO is supported)
+ * 1 if the device supports BACO;
+ * 3 if the device supports MACO (only works if BACO is supported)
  * otherwise return 0.
  */
 int amdgpu_device_supports_baco(struct drm_device *dev)
@@ -577,7 +577,7 @@ void amdgpu_device_mm_access(struct amdg
 }
 
 /**
- * amdgpu_device_aper_access - access vram by vram aperature
+ * amdgpu_device_aper_access - access vram by vram aperture
  *
  * @adev: amdgpu_device pointer
  * @pos: offset of the buffer in vram
@@ -668,7 +668,7 @@ bool amdgpu_device_skip_hw_access(struct
         * here is that the GPU reset is not running on another thread in 
parallel.
         *
         * For this we trylock the read side of the reset semaphore, if that 
succeeds
-        * we know that the reset is not running in paralell.
+        * we know that the reset is not running in parallel.
         *
         * If the trylock fails we assert that we are either already holding 
the read
         * side of the lock or are the reset thread itself and hold the write 
side of
@@ -1733,7 +1733,7 @@ bool amdgpu_device_need_post(struct amdg
                        uint32_t fw_ver;
 
                        err = request_firmware(&adev->pm.fw, 
"amdgpu/fiji_smc.bin", adev->dev);
-                       /* force vPost if error occured */
+                       /* force vPost if error occurred */
                        if (err)
                                return true;
 
@@ -2378,7 +2378,7 @@ int amdgpu_device_ip_block_add(struct am
  * the module parameter virtual_display.  This feature provides a virtual
  * display hardware on headless boards or in virtualized environments.
  * This function parses and validates the configuration string specified by
- * the user and configues the virtual display configuration (number of
+ * the user and configures the virtual display configuration (number of
  * virtual connectors, crtcs, etc.) specified.
  */
 static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev)
@@ -2441,7 +2441,7 @@ void amdgpu_device_set_sriov_virtual_dis
  * @adev: amdgpu_device pointer
  *
  * Parses the asic configuration parameters specified in the gpu info
- * firmware and makes them availale to the driver for use in configuring
+ * firmware and makes them available to the driver for use in configuring
  * the asic.
  * Returns 0 on success, -EINVAL on failure.
  */
@@ -2501,7 +2501,7 @@ static int amdgpu_device_parse_gpu_info_
                                                                
le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 
                /*
-                * Should be droped when DAL no longer needs it.
+                * Should be dropped when DAL no longer needs it.
                 */
                if (adev->asic_type == CHIP_NAVI12)
                        goto parse_soc_bounding_box;
@@ -3061,7 +3061,7 @@ init_failed:
  *
  * Writes a reset magic value to the gart pointer in VRAM.  The driver calls
  * this function before a GPU reset.  If the value is retained after a
- * GPU reset, VRAM has not been lost.  Some GPU resets may destry VRAM 
contents.
+ * GPU reset, VRAM has not been lost. Some GPU resets may destroy VRAM 
contents.
  */
 static void amdgpu_device_fill_reset_magic(struct amdgpu_device *adev)
 {
@@ -3376,7 +3376,7 @@ static int amdgpu_device_ip_fini_early(s
 
        amdgpu_amdkfd_suspend(adev, false);
 
-       /* Workaroud for ASICs need to disable SMC first */
+       /* Workaround for ASICs need to disable SMC first */
        amdgpu_device_smu_fini_early(adev);
 
        for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
@@ -4271,7 +4271,7 @@ int amdgpu_device_init(struct amdgpu_dev
 
        /*
         * Reset domain needs to be present early, before XGMI hive discovered
-        * (if any) and intitialized to use reset sem and in_gpu reset flag
+        * (if any) and initialized to use reset sem and in_gpu reset flag
         * early on during init and before calling to RREG32.
         */
        adev->reset_domain = amdgpu_reset_create_reset_domain(SINGLE_DEVICE, 
"amdgpu-reset-dev");
@@ -5862,7 +5862,7 @@ int amdgpu_device_gpu_recover(struct amd
                amdgpu_amdkfd_pre_reset(tmp_adev, reset_context);
 
                /*
-                * Mark these ASICs to be reseted as untracked first
+                * Mark these ASICs to be reset as untracked first
                 * And add them back after reset completed
                 */
                amdgpu_unregister_gpu_instance(tmp_adev);
@@ -6065,7 +6065,7 @@ static void amdgpu_device_partner_bandwi
  *
  * @adev: amdgpu_device pointer
  *
- * Fetchs and stores in the driver the PCIE capabilities (gen speed
+ * Fetches and stores in the driver the PCIE capabilities (gen speed
  * and lanes) of the slot the device is in. Handles APUs and
  * virtualized environments where PCIE config space may not be available.
  */

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