On 10/09/2024, Marek Vasut wrote:
> The media_ldb_root_clk supply LDB serializer. These clock are usually
> shared with the LCDIFv3 pixel clock and supplied by the Video PLL on
> i.MX8MP, but the LDB clock run at either x7 or x14 rate of the LCDIFv3
> pixel clock. Allow the LDB to reconfigure Video PLL as needed, as that
> results in accurate serializer clock.
>
> Signed-off-by: Marek Vasut <ma...@denx.de>
> ---
> Cc: Abel Vesa <abelv...@kernel.org>
> Cc: Andrzej Hajda <andrzej.ha...@intel.com>
> Cc: David Airlie <airl...@gmail.com>
> Cc: Fabio Estevam <feste...@gmail.com>
> Cc: Isaac Scott <isaac.sc...@ideasonboard.com>
> Cc: Jernej Skrabec <jernej.skra...@gmail.com>
> Cc: Jonas Karlman <jo...@kwiboo.se>
> Cc: Laurent Pinchart <laurent.pinch...@ideasonboard.com>
> Cc: Maarten Lankhorst <maarten.lankho...@linux.intel.com>
> Cc: Maxime Ripard <mrip...@kernel.org>
> Cc: Michael Turquette <mturque...@baylibre.com>
> Cc: Neil Armstrong <neil.armstr...@linaro.org>
> Cc: Peng Fan <peng....@nxp.com>
> Cc: Pengutronix Kernel Team <ker...@pengutronix.de>
> Cc: Robert Foss <rf...@kernel.org>
> Cc: Sascha Hauer <s.ha...@pengutronix.de>
> Cc: Shawn Guo <shawn...@kernel.org>
> Cc: Simona Vetter <sim...@ffwll.ch>
> Cc: Stephen Boyd <sb...@kernel.org>
> Cc: Thomas Zimmermann <tzimmerm...@suse.de>
> Cc: dri-devel@lists.freedesktop.org
> Cc: i...@lists.linux.dev
> Cc: ker...@dh-electronics.com
> Cc: linux-arm-ker...@lists.infradead.org
> Cc: linux-...@vger.kernel.org
> ---
> drivers/clk/imx/clk-imx8mp.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
> index 516dbd170c8a3..2e61d340b8ab7 100644
> --- a/drivers/clk/imx/clk-imx8mp.c
> +++ b/drivers/clk/imx/clk-imx8mp.c
> @@ -611,7 +611,7 @@ static int imx8mp_clocks_probe(struct platform_device
> *pdev)
> hws[IMX8MP_CLK_MEDIA_MIPI_PHY1_REF] =
> imx8m_clk_hw_composite("media_mipi_phy1_ref",
> imx8mp_media_mipi_phy1_ref_sels, ccm_base + 0xbd80);
> hws[IMX8MP_CLK_MEDIA_DISP1_PIX] =
> imx8m_clk_hw_composite_bus_flags("media_disp1_pix",
> imx8mp_media_disp_pix_sels, ccm_base + 0xbe00, CLK_SET_RATE_PARENT);
> hws[IMX8MP_CLK_MEDIA_CAM2_PIX] =
> imx8m_clk_hw_composite("media_cam2_pix", imx8mp_media_cam2_pix_sels, ccm_base
> + 0xbe80);
> - hws[IMX8MP_CLK_MEDIA_LDB] = imx8m_clk_hw_composite("media_ldb",
> imx8mp_media_ldb_sels, ccm_base + 0xbf00);
> + hws[IMX8MP_CLK_MEDIA_LDB] =
> imx8m_clk_hw_composite_bus_flags("media_ldb", imx8mp_media_ldb_sels, ccm_base
> + 0xbf00, CLK_SET_RATE_PARENT);
This patch would cause the below in-flight LDB bridge driver
patch[1] fail to do display mode validation upon display modes
read from LVDS to HDMI converter IT6263's DDC I2C bus.
Unsupported display modes cannot be ruled out. Note that
"media_ldb" is derived from "video_pll1_out" by default as the
parent is set in imx8mp.dtsi. And, the only 4 rates supported
by "video_pll1" are listed in imx_pll1443x_tbl[] - 1.0395GHz,
650MHz, 594MHz and 519.75MHz.
[1] https://patchwork.freedesktop.org/patch/616907/?series=139266&rev=1
> hws[IMX8MP_CLK_MEMREPAIR] =
> imx8m_clk_hw_composite_critical("mem_repair", imx8mp_memrepair_sels, ccm_base
> + 0xbf80);
> hws[IMX8MP_CLK_MEDIA_MIPI_TEST_BYTE] =
> imx8m_clk_hw_composite("media_mipi_test_byte",
> imx8mp_media_mipi_test_byte_sels, ccm_base + 0xc100);
> hws[IMX8MP_CLK_ECSPI3] = imx8m_clk_hw_composite("ecspi3",
> imx8mp_ecspi3_sels, ccm_base + 0xc180);
--
Regards,
Liu Ying
