> -----Original Message-----
> From: Kaustabh Chakraborty <kauschl...@disroot.org>
> Sent: Friday, September 20, 2024 12:11 AM
> To: Inki Dae <inki....@samsung.com>; Seung-Woo Kim
> <sw0312....@samsung.com>; Kyungmin Park <kyungmin.p...@samsung.com>; David
> Airlie <airl...@gmail.com>; Simona Vetter <sim...@ffwll.ch>; Krzysztof
> Kozlowski <k...@kernel.org>; Alim Akhtar <alim.akh...@samsung.com>;
> Maarten Lankhorst <maarten.lankho...@linux.intel.com>; Maxime Ripard
> <mrip...@kernel.org>; Thomas Zimmermann <tzimmerm...@suse.de>; Rob Herring
> <r...@kernel.org>; Conor Dooley <co...@kernel.org>
> Cc: dri-devel@lists.freedesktop.org; linux-arm-ker...@lists.infradead.org;
> linux-samsung-...@vger.kernel.org; linux-ker...@vger.kernel.org;
> devicet...@vger.kernel.org; Kaustabh Chakraborty <kauschl...@disroot.org>
> Subject: [PATCH 3/6] drm/exynos: exynos7_drm_decon: fix ideal_clk by
> converting it to Hz
>
> The clkdiv values are incorrect as ideal_clk is in kHz and the clock
> rate of vclk is in Hz. Multiply 1000 to ideal_clk to bring it to Hz.
>
> Signed-off-by: Kaustabh Chakraborty <kauschl...@disroot.org>
> ---
> drivers/gpu/drm/exynos/exynos7_drm_decon.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/exynos/exynos7_drm_decon.c
> b/drivers/gpu/drm/exynos/exynos7_drm_decon.c
> index 2c4ee87ae6ec..4e4ced50ff15 100644
> --- a/drivers/gpu/drm/exynos/exynos7_drm_decon.c
> +++ b/drivers/gpu/drm/exynos/exynos7_drm_decon.c
> @@ -137,7 +137,7 @@ static void decon_ctx_remove(struct decon_context *ctx)
> static u32 decon_calc_clkdiv(struct decon_context *ctx,
> const struct drm_display_mode *mode)
> {
> - unsigned long ideal_clk = mode->clock;
> + unsigned long ideal_clk = mode->clock * 1000;
Right. ideal_clk should be fixed with Hz.
Thanks,
Inki Dae
> u32 clkdiv;
>
> /* Find the clock divider value that gets us closest to ideal_clk
> */
>
> --
> 2.46.1
