On Thu, Sep 26, 2024 at 04:31:37PM GMT, Mahadevan wrote:
> Add mdss0 and mdp devicetree nodes for sa8775p target.
>
> Signed-off-by: Mahadevan <quic_ma...@quicinc.com>
>
> ---
>
> This patch depends on the clock enablement change:
> https://lore.kernel.org/all/20240816-sa8775p-mm-v3-v1-0-77d53c3c0...@quicinc.com/
>
> ---
>
> [v2]
> - Update commit message mentioning enablement of mdss0 only is done. [Dmitry]
It doesn't
> - Add resets node and fix indentation. [Dmitry]
> ---
> arch/arm64/boot/dts/qcom/sa8775p.dtsi | 87 +++++++++++++++++++++++++++
> 1 file changed, 87 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> index 93be4683a31f..27ab1921c1f3 100644
> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> @@ -6,6 +6,7 @@
> #include <dt-bindings/interconnect/qcom,icc.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/clock/qcom,rpmh.h>
> +#include <dt-bindings/clock/qcom,sa8775p-dispcc.h>
> #include <dt-bindings/clock/qcom,sa8775p-gcc.h>
> #include <dt-bindings/clock/qcom,sa8775p-gpucc.h>
> #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
> @@ -2937,6 +2938,92 @@ camcc: clock-controller@ade0000 {
> #power-domain-cells = <1>;
> };
>
> + mdss0: display-subsystem@ae00000 {
> + compatible = "qcom,sa8775p-mdss";
> + reg = <0x0 0x0ae00000 0x0 0x1000>;
> + reg-names = "mdss";
> +
> + /* same path used twice */
> + interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt
> SLAVE_EBI1 0>,
> + <&mmss_noc MASTER_MDP1 0 &mc_virt
> SLAVE_EBI1 0>,
QCOM_ICC_TAG_ACTIVE_ONLY ?
> + <&gem_noc MASTER_APPSS_PROC
> QCOM_ICC_TAG_ACTIVE_ONLY
> + &config_noc SLAVE_DISPLAY_CFG
> QCOM_ICC_TAG_ACTIVE_ONLY>;
> + interconnect-names = "mdp0-mem",
> + "mdp1-mem",
> + "cpu-cfg";
> +
> + resets = <&dispcc0 MDSS_DISP_CC_MDSS_CORE_BCR>;
> +
> + power-domains = <&dispcc0 MDSS_DISP_CC_MDSS_CORE_GDSC>;
> +
> + clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
> + <&gcc GCC_DISP_HF_AXI_CLK>,
> + <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>;
> +
> + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> +
> + iommus = <&apps_smmu 0x1000 0x402>;
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + status = "disabled";
> +
> + mdss0_mdp: display-controller@ae01000 {
> + compatible = "qcom,sa8775p-dpu";
> + reg = <0x0 0x0ae01000 0x0 0x8f000>,
> + <0x0 0x0aeb0000 0x0 0x2008>;
> + reg-names = "mdp", "vbif";
> +
> + clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
> + <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc0
> MDSS_DISP_CC_MDSS_MDP_LUT_CLK>,
> + <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>,
> + <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>;
> + clock-names = "bus",
> + "iface",
> + "lut",
> + "core",
> + "vsync";
> +
> + assigned-clocks = <&dispcc0
> MDSS_DISP_CC_MDSS_VSYNC_CLK>;
> + assigned-clock-rates = <19200000>;
> +
> + operating-points-v2 = <&mdss0_mdp_opp_table>;
> + power-domains = <&rpmhpd RPMHPD_MMCX>;
> +
> + interrupt-parent = <&mdss0>;
> + interrupts = <0>;
> +
> + mdss0_mdp_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-375000000 {
> + opp-hz = /bits/ 64 <375000000>;
> + required-opps =
> <&rpmhpd_opp_svs_l1>;
> + };
> +
> + opp-500000000 {
> + opp-hz = /bits/ 64 <500000000>;
> + required-opps =
> <&rpmhpd_opp_nom>;
> + };
> +
> + opp-575000000 {
> + opp-hz = /bits/ 64 <575000000>;
> + required-opps =
> <&rpmhpd_opp_turbo>;
> + };
> +
> + opp-650000000 {
> + opp-hz = /bits/ 64 <650000000>;
> + required-opps =
> <&rpmhpd_opp_turbo_l1>;
> + };
> + };
> + };
> + };
> +
> dispcc0: clock-controller@af00000 {
> compatible = "qcom,sa8775p-dispcc0";
> reg = <0x0 0x0af00000 0x0 0x20000>;
> --
> 2.34.1
>
--
With best wishes
Dmitry
