Hi Biju,
Thank you for the patch.
On Tue, Jul 09, 2024 at 02:51:44PM +0100, Biju Das wrote:
> Add vspd node to RZ/G2UL SoC DTSI.
>
> Signed-off-by: Biju Das <biju.das...@bp.renesas.com>
> ---
> v1->v2:
> * No change.
> ---
> arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
> b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
> index 18ef297db933..15e84a5428ef 100644
> --- a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
> @@ -129,6 +129,19 @@ csi2cru: endpoint@0 {
> };
> };
>
> + vspd: vsp@10870000 {
> + compatible = "renesas,r9a07g043u-vsp2",
> "renesas,r9a07g044-vsp2";
> + reg = <0 0x10870000 0 0x10000>;
> + interrupts = <SOC_PERIPHERAL_IRQ(149) IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD R9A07G043_LCDC_CLK_A>,
> + <&cpg CPG_MOD R9A07G043_LCDC_CLK_P>,
> + <&cpg CPG_MOD R9A07G043_LCDC_CLK_D>;
> + clock-names = "aclk", "pclk", "vclk";
> + power-domains = <&cpg>;
> + resets = <&cpg R9A07G043_LCDC_RESET_N>;
> + renesas,fcp = <&fcpvd>;
This patch looks fine, but I would move it after 7/9, as here you
reference a node that doesn't exist yet.
Reviewed-by: Laurent Pinchart <laurent.pinchart+rene...@ideasonboard.com>
> + };
> +
> irqc: interrupt-controller@110a0000 {
> compatible = "renesas,r9a07g043u-irqc",
> "renesas,rzg2l-irqc";
--
Regards,
Laurent Pinchart
