On 22/06/2024 14:09, Aradhya Bhatia wrote:
The order of init of DSI link and DSI phy is wrong. The DSI link needs to be configured before the DSI phy is getting configured. Otherwise, the D-Phy is unable to lock in on the incoming PLL Reference clock[0].Fix the order of inits. [0]: See section 12.6.5.7.3 "Start-up Procedure" in J721E SoC TRM TRM Link: http://www.ti.com/lit/pdf/spruil1 Fixes: fced5a364dee ("drm/bridge: cdns: Convert to phy framework") Signed-off-by: Aradhya Bhatia <a-bhat...@ti.com> --- drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c index d89c32bae2b9..03a5af52ec0b 100644 --- a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c +++ b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c @@ -778,8 +778,8 @@ static void cdns_dsi_bridge_enable(struct drm_bridge *bridge)WARN_ON_ONCE(cdns_dsi_check_conf(dsi, mode, &dsi_cfg, false)); - cdns_dsi_hs_init(dsi);cdns_dsi_init_link(dsi); + cdns_dsi_hs_init(dsi);writel(HBP_LEN(dsi_cfg.hbp) | HSA_LEN(dsi_cfg.hsa),dsi->regs + VID_HSIZE1);
Reviewed-by: Tomi Valkeinen <tomi.valkei...@ideasonboard.com> Tomi
