Am Sonntag, 23. Juni 2024, 16:38:37 CEST schrieb Marek Vasut:
> The only information in the datasheet regarding this divider is a note
> in SYS_PLLPARAM register documentation which states that when LSCLK is
> 270 MHz, LSCLK_DIV should be 1. What should LSCLK_DIV be set to when
> LSCLK is 162 MHz (for DP 1.62G mode) is unclear, but empirical test
> confirms using LSCLK_DIV 1 has no adverse effects either. In the worst
> case, the internal TC358767 clock would run faster.
>
> Signed-off-by: Marek Vasut <ma...@denx.de>
Works also on a 2.7Gbps link.
Reviewed-by: Alexander Stein <alexander.st...@ew.tq-group.com>
> ---
> Cc: Andrzej Hajda <andrzej.ha...@intel.com>
> Cc: Daniel Vetter <dan...@ffwll.ch>
> Cc: David Airlie <airl...@gmail.com>
> Cc: Jernej Skrabec <jernej.skra...@gmail.com>
> Cc: Jonas Karlman <jo...@kwiboo.se>
> Cc: Laurent Pinchart <laurent.pinch...@ideasonboard.com>
> Cc: Lucas Stach <l.st...@pengutronix.de>
> Cc: Maarten Lankhorst <maarten.lankho...@linux.intel.com>
> Cc: Maxime Ripard <mrip...@kernel.org>
> Cc: Neil Armstrong <neil.armstr...@linaro.org>
> Cc: Robert Foss <rf...@kernel.org>
> Cc: Thomas Zimmermann <tzimmerm...@suse.de>
> Cc: dri-devel@lists.freedesktop.org
> Cc: ker...@dh-electronics.com
> ---
> V2: No change
> V3: No change
> ---
> drivers/gpu/drm/bridge/tc358767.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/bridge/tc358767.c
> b/drivers/gpu/drm/bridge/tc358767.c
> index a48454fe2f634..743bf1334923d 100644
> --- a/drivers/gpu/drm/bridge/tc358767.c
> +++ b/drivers/gpu/drm/bridge/tc358767.c
> @@ -738,7 +738,7 @@ static int tc_stream_clock_calc(struct tc_data *tc)
> static int tc_set_syspllparam(struct tc_data *tc)
> {
> unsigned long rate;
> - u32 pllparam = SYSCLK_SEL_LSCLK | LSCLK_DIV_2;
> + u32 pllparam = SYSCLK_SEL_LSCLK | LSCLK_DIV_1;
>
> rate = clk_get_rate(tc->refclk);
> switch (rate) {
>
--
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