The MediaTek MT8173 comes with a PowerVR Rogue GX6250, which is part
of the Series6XT, another variation of the Rogue family of GPUs.
On top of the GPU is a glue layer that handles some clock and power
signals.
Add device nodes for both.
Signed-off-by: Chen-Yu Tsai <we...@chromium.org>
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 136b28f80cc2..3d7b9cc20a16 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -993,6 +993,30 @@ u2port1: usb-phy@11291000 {
};
};
+ gpu: gpu@13000000 {
+ compatible = "mediatek,mt8173-gpu", "img,powervr-6xt";
+ reg = <0 0x13000000 0 0x10000>;
+ interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&mfgtop CLK_MFG_G3D>,
+ <&mfgtop CLK_MFG_MEM>,
+ <&mfgtop CLK_MFG_AXI>;
+ clock-names = "core", "mem", "sys";
+ power-domains = <&mfgtop>;
+ };
+
+ mfgtop: clock-controller@13fff000 {
+ compatible = "mediatek,mt8173-mfgtop";
+ reg = <0 0x13fff000 0 0x1000>;
+ clocks = <&topckgen CLK_TOP_AXI_MFG_IN_SEL>,
+ <&topckgen CLK_TOP_MEM_MFG_IN_SEL>,
+ <&topckgen CLK_TOP_MFG_SEL>,
+ <&clk26m>;
+ clock-names = "sys", "mem", "core", "clk26m";
+ power-domains = <&spm MT8173_POWER_DOMAIN_MFG>;
+ #clock-cells = <1>;
+ #power-domain-cells = <0>;
+ };
+
mmsys: syscon@14000000 {
compatible = "mediatek,mt8173-mmsys", "syscon";
reg = <0 0x14000000 0 0x1000>;
--
2.45.1.288.g0e0cd299f1-goog
