Setting the link bandwidth may change the PLL parameters, which will cause
the PLL to go out of lock, so make sure to apply the MACRO_RST, which
according to the comment is required to be pulsed after the PLL is locked.

Signed-off-by: Lucas Stach <l.st...@pengutronix.de>
---
 .../gpu/drm/bridge/analogix/analogix_dp_core.c | 18 ++++++++++--------
 1 file changed, 10 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c 
b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index b4a47311cfe8..736b2ed745e1 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -243,6 +243,11 @@ static int analogix_dp_link_start(struct 
analogix_dp_device *dp)
 
        /* Set link rate and count as you want to establish*/
        analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
+       /*
+        * MACRO_RST must be applied after the PLL_LOCK to avoid
+        * the DP inter pair skew issue for at least 10 us
+        */
+       analogix_dp_reset_macro(dp);
        analogix_dp_set_lane_count(dp, dp->link_train.lane_count);
 
        /* Setup RX configuration */
@@ -565,12 +570,6 @@ static int analogix_dp_full_link_train(struct 
analogix_dp_device *dp,
        int retval = 0;
        bool training_finished = false;
 
-       /*
-        * MACRO_RST must be applied after the PLL_LOCK to avoid
-        * the DP inter pair skew issue for at least 10 us
-        */
-       analogix_dp_reset_macro(dp);
-
        /* Initialize by reading RX's DPCD */
        analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
        analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
@@ -637,9 +636,12 @@ static int analogix_dp_fast_link_train(struct 
analogix_dp_device *dp)
        u8 link_align, link_status[2];
        enum pll_status status;
 
-       analogix_dp_reset_macro(dp);
-
        analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
+       /*
+        * MACRO_RST must be applied after the PLL_LOCK to avoid
+        * the DP inter pair skew issue for at least 10 us
+        */
+       analogix_dp_reset_macro(dp);
        analogix_dp_set_lane_count(dp, dp->link_train.lane_count);
        analogix_dp_set_lane_link_training(dp);
 
-- 
2.39.2

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