[PATCH 06/10] arm64: dts: qcom: sm8550: Add UART15

[Xilin Wu via B4 Relay]

From: Xilin Wu <wuxilin...@gmail.com>

Add uart15 node for UART bus present on sm8550 SoC.

Signed-off-by: Molly Sophia <mollysophia...@gmail.com>
Signed-off-by: Xilin Wu <wuxilin...@gmail.com>
---
 arch/arm64/boot/dts/qcom/sm8550.dtsi | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi 
b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index bc5aeb05ffc3..b8bbe88e770f 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -1122,6 +1122,20 @@ spi15: spi@89c000 {
                                #size-cells = <0>;
                                status = "disabled";
                        };
+
+                       uart15: serial@89c000 {
+                               compatible = "qcom,geni-uart";
+                               reg = <0 0x89c000 0 0x4000>;
+                               clock-names = "se";
+                               clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&qup_uart15_default>;
+                               interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
+                               interconnects = <&clk_virt MASTER_QUP_CORE_2 0 
&clk_virt SLAVE_QUP_CORE_2 0>,
+                                               <&gem_noc MASTER_APPSS_PROC 0 
&config_noc SLAVE_QUP_2 0>;
+                               interconnect-names = "qup-core", "qup-config";
+                               status = "disabled";
+                       };
                };
 
                i2c_master_hub_0: geniqup@9c0000 {
@@ -3856,6 +3870,14 @@ qup_uart14_cts_rts: qup-uart14-cts-rts-state {
                                bias-pull-down;
                        };
 
+                       qup_uart15_default: qup-uart15-default-state {
+                               /* TX, RX */
+                               pins = "gpio74", "gpio75";
+                               function = "qup2_se7";
+                               drive-strength = <2>;
+                               bias-pull-up;
+                       };
+
                        sdc2_sleep: sdc2-sleep-state {
                                clk-pins {
                                        pins = "sdc2_clk";

-- 
2.44.0