From: Sam Ravnborg <s...@ravnborg.org>
Drop the sun4m and sun4d code from trampoline_32
Signed-off-by: Sam Ravnborg <s...@ravnborg.org>
Cc: "David S. Miller" <da...@davemloft.net>
Cc: Arnd Bergmann <a...@kernel.org>
Cc: Andreas Larsson <andr...@gaisler.com>
---
arch/sparc/kernel/kernel.h | 3 +-
arch/sparc/kernel/trampoline_32.S | 127 +-------------------------------------
2 files changed, 3 insertions(+), 127 deletions(-)
diff --git a/arch/sparc/kernel/kernel.h b/arch/sparc/kernel/kernel.h
index 30adbec894f7..aea96b6b881c 100644
--- a/arch/sparc/kernel/kernel.h
+++ b/arch/sparc/kernel/kernel.h
@@ -112,8 +112,7 @@ extern unsigned int real_irq_entry[];
extern unsigned int smp4d_ticker[];
/* trampoline_32.S */
-extern unsigned long sun4m_cpu_startup;
-extern unsigned long sun4d_cpu_startup;
+void leon_smp_cpu_startup(int boot_cpu);
/* signal_32.c */
asmlinkage void do_sigreturn(struct pt_regs *regs);
diff --git a/arch/sparc/kernel/trampoline_32.S
b/arch/sparc/kernel/trampoline_32.S
index 82fafeeb3a62..685b20923f6b 100644
--- a/arch/sparc/kernel/trampoline_32.S
+++ b/arch/sparc/kernel/trampoline_32.S
@@ -15,136 +15,12 @@
#include <asm/contregs.h>
#include <asm/thread_info.h>
- .globl sun4m_cpu_startup
- .globl sun4d_cpu_startup
-
- .align 4
-
/* When we start up a cpu for the first time it enters this routine.
* This initializes the chip from whatever state the prom left it
* in and sets PIL in %psr to 15, no irqs.
*/
-
-sun4m_cpu_startup:
-cpu1_startup:
- sethi %hi(trapbase_cpu1), %g3
- b 1f
- or %g3, %lo(trapbase_cpu1), %g3
-
-cpu2_startup:
- sethi %hi(trapbase_cpu2), %g3
- b 1f
- or %g3, %lo(trapbase_cpu2), %g3
-
-cpu3_startup:
- sethi %hi(trapbase_cpu3), %g3
- b 1f
- or %g3, %lo(trapbase_cpu3), %g3
-
-1:
- /* Set up a sane %psr -- PIL<0xf> S<0x1> PS<0x1> CWP<0x0> */
- set (PSR_PIL | PSR_S | PSR_PS), %g1
- wr %g1, 0x0, %psr ! traps off though
- WRITE_PAUSE
-
- /* Our %wim is one behind CWP */
- mov 2, %g1
- wr %g1, 0x0, %wim
- WRITE_PAUSE
-
- /* This identifies "this cpu". */
- wr %g3, 0x0, %tbr
- WRITE_PAUSE
-
- /* Give ourselves a stack and curptr. */
- set current_set, %g5
- srl %g3, 10, %g4
- and %g4, 0xc, %g4
- ld [%g5 + %g4], %g6
-
- sethi %hi(THREAD_SIZE - STACKFRAME_SZ), %sp
- or %sp, %lo(THREAD_SIZE - STACKFRAME_SZ), %sp
- add %g6, %sp, %sp
-
- /* Turn on traps (PSR_ET). */
- rd %psr, %g1
- wr %g1, PSR_ET, %psr ! traps on
- WRITE_PAUSE
-
- /* Init our caches, etc. */
- set poke_srmmu, %g5
- ld [%g5], %g5
- call %g5
- nop
-
- /* Start this processor. */
- call smp_callin
- nop
-
- b,a smp_panic
-
.text
.align 4
-
-smp_panic:
- call cpu_panic
- nop
-
-/* CPUID in bootbus can be found at PA 0xff0140000 */
-#define SUN4D_BOOTBUS_CPUID 0xf0140000
-
- .align 4
-
-sun4d_cpu_startup:
- /* Set up a sane %psr -- PIL<0xf> S<0x1> PS<0x1> CWP<0x0> */
- set (PSR_PIL | PSR_S | PSR_PS), %g1
- wr %g1, 0x0, %psr ! traps off though
- WRITE_PAUSE
-
- /* Our %wim is one behind CWP */
- mov 2, %g1
- wr %g1, 0x0, %wim
- WRITE_PAUSE
-
- /* Set tbr - we use just one trap table. */
- set trapbase, %g1
- wr %g1, 0x0, %tbr
- WRITE_PAUSE
-
- /* Get our CPU id out of bootbus */
- set SUN4D_BOOTBUS_CPUID, %g3
- lduba [%g3] ASI_M_CTL, %g3
- and %g3, 0xf8, %g3
- srl %g3, 3, %g1
- sta %g1, [%g0] ASI_M_VIKING_TMP1
-
- /* Give ourselves a stack and curptr. */
- set current_set, %g5
- srl %g3, 1, %g4
- ld [%g5 + %g4], %g6
-
- sethi %hi(THREAD_SIZE - STACKFRAME_SZ), %sp
- or %sp, %lo(THREAD_SIZE - STACKFRAME_SZ), %sp
- add %g6, %sp, %sp
-
- /* Turn on traps (PSR_ET). */
- rd %psr, %g1
- wr %g1, PSR_ET, %psr ! traps on
- WRITE_PAUSE
-
- /* Init our caches, etc. */
- set poke_srmmu, %g5
- ld [%g5], %g5
- call %g5
- nop
-
- /* Start this processor. */
- call smp_callin
- nop
-
- b,a smp_panic
-
- .align 4
.global leon_smp_cpu_startup, smp_penguin_ctable
leon_smp_cpu_startup:
@@ -198,4 +74,5 @@ leon_smp_cpu_startup:
call smp_callin
nop
- b,a smp_panic
+ b,a cpu_panic
+ nop
--
2.34.1
