There are no in-kernel users of MSM_ENC_VBLANK wait type. Drop it
together with the corresponding wait_for_vblank callback.

Signed-off-by: Dmitry Baryshkov <dmitry.barysh...@linaro.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c   |  3 --
 .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h  |  1 -
 .../drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c  | 28 -------------------
 .../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c  |  9 +++---
 drivers/gpu/drm/msm/msm_drv.h                 |  2 --
 5 files changed, 4 insertions(+), 39 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index d34e684a4178..83045aa8ba01 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -2429,9 +2429,6 @@ int dpu_encoder_wait_for_event(struct drm_encoder 
*drm_enc,
                case MSM_ENC_TX_COMPLETE:
                        fn_wait = phys->ops.wait_for_tx_complete;
                        break;
-               case MSM_ENC_VBLANK:
-                       fn_wait = phys->ops.wait_for_vblank;
-                       break;
                default:
                        DPU_ERROR_ENC(dpu_enc, "unknown wait event %d\n",
                                        event);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
index d48558ede488..c6cccab3bb6d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
@@ -106,7 +106,6 @@ struct dpu_encoder_phys_ops {
        int (*control_vblank_irq)(struct dpu_encoder_phys *enc, bool enable);
        int (*wait_for_commit_done)(struct dpu_encoder_phys *phys_enc);
        int (*wait_for_tx_complete)(struct dpu_encoder_phys *phys_enc);
-       int (*wait_for_vblank)(struct dpu_encoder_phys *phys_enc);
        void (*prepare_for_kickoff)(struct dpu_encoder_phys *phys_enc);
        void (*handle_post_kickoff)(struct dpu_encoder_phys *phys_enc);
        void (*trigger_start)(struct dpu_encoder_phys *phys_enc);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
index df88358e7037..285246837b73 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
@@ -690,33 +690,6 @@ static int dpu_encoder_phys_cmd_wait_for_commit_done(
        return _dpu_encoder_phys_cmd_wait_for_ctl_start(phys_enc);
 }
 
-static int dpu_encoder_phys_cmd_wait_for_vblank(
-               struct dpu_encoder_phys *phys_enc)
-{
-       int rc = 0;
-       struct dpu_encoder_phys_cmd *cmd_enc;
-       struct dpu_encoder_wait_info wait_info;
-
-       cmd_enc = to_dpu_encoder_phys_cmd(phys_enc);
-
-       /* only required for master controller */
-       if (!dpu_encoder_phys_cmd_is_master(phys_enc))
-               return rc;
-
-       wait_info.wq = &cmd_enc->pending_vblank_wq;
-       wait_info.atomic_cnt = &cmd_enc->pending_vblank_cnt;
-       wait_info.timeout_ms = KICKOFF_TIMEOUT_MS;
-
-       atomic_inc(&cmd_enc->pending_vblank_cnt);
-
-       rc = dpu_encoder_helper_wait_for_irq(phys_enc,
-                       phys_enc->irq[INTR_IDX_RDPTR],
-                       dpu_encoder_phys_cmd_te_rd_ptr_irq,
-                       &wait_info);
-
-       return rc;
-}
-
 static void dpu_encoder_phys_cmd_handle_post_kickoff(
                struct dpu_encoder_phys *phys_enc)
 {
@@ -745,7 +718,6 @@ static void dpu_encoder_phys_cmd_init_ops(
        ops->wait_for_commit_done = dpu_encoder_phys_cmd_wait_for_commit_done;
        ops->prepare_for_kickoff = dpu_encoder_phys_cmd_prepare_for_kickoff;
        ops->wait_for_tx_complete = dpu_encoder_phys_cmd_wait_for_tx_complete;
-       ops->wait_for_vblank = dpu_encoder_phys_cmd_wait_for_vblank;
        ops->trigger_start = dpu_encoder_phys_cmd_trigger_start;
        ops->needs_single_flush = dpu_encoder_phys_cmd_needs_single_flush;
        ops->irq_control = dpu_encoder_phys_cmd_irq_control;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c 
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index c2189e58de6a..94521f6d7f70 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -444,7 +444,7 @@ static void dpu_encoder_phys_vid_destroy(struct 
dpu_encoder_phys *phys_enc)
        kfree(phys_enc);
 }
 
-static int dpu_encoder_phys_vid_wait_for_vblank(
+static int dpu_encoder_phys_vid_wait_for_tx_complete(
                struct dpu_encoder_phys *phys_enc)
 {
        struct dpu_encoder_wait_info wait_info;
@@ -558,7 +558,7 @@ static void dpu_encoder_phys_vid_disable(struct 
dpu_encoder_phys *phys_enc)
         * scanout buffer) don't latch properly..
         */
        if (dpu_encoder_phys_vid_is_master(phys_enc)) {
-               ret = dpu_encoder_phys_vid_wait_for_vblank(phys_enc);
+               ret = dpu_encoder_phys_vid_wait_for_tx_complete(phys_enc);
                if (ret) {
                        atomic_set(&phys_enc->pending_kickoff_cnt, 0);
                        DRM_ERROR("wait disable failed: id:%u intf:%d ret:%d\n",
@@ -578,7 +578,7 @@ static void dpu_encoder_phys_vid_disable(struct 
dpu_encoder_phys *phys_enc)
                spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
                dpu_encoder_phys_inc_pending(phys_enc);
                spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
-               ret = dpu_encoder_phys_vid_wait_for_vblank(phys_enc);
+               ret = dpu_encoder_phys_vid_wait_for_tx_complete(phys_enc);
                if (ret) {
                        atomic_set(&phys_enc->pending_kickoff_cnt, 0);
                        DRM_ERROR("wait disable failed: id:%u intf:%d ret:%d\n",
@@ -684,8 +684,7 @@ static void dpu_encoder_phys_vid_init_ops(struct 
dpu_encoder_phys_ops *ops)
        ops->destroy = dpu_encoder_phys_vid_destroy;
        ops->control_vblank_irq = dpu_encoder_phys_vid_control_vblank_irq;
        ops->wait_for_commit_done = dpu_encoder_phys_vid_wait_for_commit_done;
-       ops->wait_for_vblank = dpu_encoder_phys_vid_wait_for_vblank;
-       ops->wait_for_tx_complete = dpu_encoder_phys_vid_wait_for_vblank;
+       ops->wait_for_tx_complete = dpu_encoder_phys_vid_wait_for_tx_complete;
        ops->irq_control = dpu_encoder_phys_vid_irq_control;
        ops->prepare_for_kickoff = dpu_encoder_phys_vid_prepare_for_kickoff;
        ops->handle_post_kickoff = dpu_encoder_phys_vid_handle_post_kickoff;
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index 02fd6c7d0bb7..182543c92770 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -78,12 +78,10 @@ enum msm_dsi_controller {
  * enum msm_event_wait - type of HW events to wait for
  * @MSM_ENC_COMMIT_DONE - wait for the driver to flush the registers to HW
  * @MSM_ENC_TX_COMPLETE - wait for the HW to transfer the frame to panel
- * @MSM_ENC_VBLANK - wait for the HW VBLANK event (for driver-internal waiters)
  */
 enum msm_event_wait {
        MSM_ENC_COMMIT_DONE = 0,
        MSM_ENC_TX_COMPLETE,
-       MSM_ENC_VBLANK,
 };
 
 /**
-- 
2.40.1

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