https://bugs.freedesktop.org/show_bug.cgi?id=69675
--- Comment #6 from Alex Deucher <ag...@yahoo.com> ---
(In reply to comment #5)
> (In reply to comment #4)
> > Something like this:
>
> Not really, the selection doesn't work like that - clock has to match
> exactly to the table value, it is not an upper bound.
I just meant to patch the table so that you end up using the pre-defined values
for CTS and N rather than calculating them from the formula.
{ xxx, 11648, 210937, 17836, 234375, 11648, 140625 }, /* 74.25/1.001 MHz */
Replace xxx with whatever clock value the drm edid code gives you for
74.25/1.001 MHz.
The's presumably a reason the predefined values are there rather just using the
formula for everything.
The actual clock generated by the PLL will not always be exact either. It's
limited by reference clock and the divider ranges.
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