From: Sui Jingfeng <suijingf...@loongson.cn>
Add a dedicate function to do the DMA configuration to the virtual master.
Also replace the &pdev->dev with dev.
Signed-off-by: Sui Jingfeng <suijingf...@loongson.cn>
---
drivers/gpu/drm/etnaviv/etnaviv_drv.c | 65 +++++++++++++++------------
1 file changed, 36 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_drv.c
b/drivers/gpu/drm/etnaviv/etnaviv_drv.c
index 47b2cdbb53e2..8907cdb8a1f8 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_drv.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_drv.c
@@ -54,6 +54,40 @@ static bool etnaviv_is_dma_coherent(struct device *dev)
return coherent;
}
+static int etnaviv_of_dma_configure(struct device *dev)
+{
+ struct device_node *first_node;
+
+ /*
+ * PTA and MTLB can have 40 bit base addresses, but
+ * unfortunately, an entry in the MTLB can only point to a
+ * 32 bit base address of a STLB. Moreover, to initialize the
+ * MMU we need a command buffer with a 32 bit address because
+ * without an MMU there is only an indentity mapping between
+ * the internal 32 bit addresses and the bus addresses.
+ *
+ * To make things easy, we set the dma_coherent_mask to 32
+ * bit to make sure we are allocating the command buffers and
+ * TLBs in the lower 4 GiB address space.
+ */
+ if (dma_set_mask(dev, DMA_BIT_MASK(40)) ||
+ dma_set_coherent_mask(dev, DMA_BIT_MASK(32))) {
+ dev_err(dev, "No suitable DMA available\n");
+ return -ENODEV;
+ }
+
+ /*
+ * Apply the same DMA configuration to the virtual etnaviv
+ * device as the GPU we found. This assumes that all Vivante
+ * GPUs in the system share the same DMA constraints.
+ */
+ first_node = etnaviv_of_first_available_node();
+ if (first_node)
+ of_dma_configure(dev, first_node, true);
+
+ return 0;
+}
+
/*
* etnaviv private data construction and destructions:
*/
@@ -664,7 +698,6 @@ static const struct component_master_ops etnaviv_master_ops
= {
static int etnaviv_pdev_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
- struct device_node *first_node = NULL;
struct component_match *match = NULL;
if (!dev->platform_data) {
@@ -674,10 +707,7 @@ static int etnaviv_pdev_probe(struct platform_device *pdev)
if (!of_device_is_available(core_node))
continue;
- if (!first_node)
- first_node = core_node;
-
- drm_of_component_match_add(&pdev->dev, &match,
+ drm_of_component_match_add(dev, &match,
component_compare_of,
core_node);
}
} else {
@@ -688,31 +718,8 @@ static int etnaviv_pdev_probe(struct platform_device *pdev)
component_match_add(dev, &match,
component_compare_dev_name, names[i]);
}
- /*
- * PTA and MTLB can have 40 bit base addresses, but
- * unfortunately, an entry in the MTLB can only point to a
- * 32 bit base address of a STLB. Moreover, to initialize the
- * MMU we need a command buffer with a 32 bit address because
- * without an MMU there is only an indentity mapping between
- * the internal 32 bit addresses and the bus addresses.
- *
- * To make things easy, we set the dma_coherent_mask to 32
- * bit to make sure we are allocating the command buffers and
- * TLBs in the lower 4 GiB address space.
- */
- if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(40)) ||
- dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32))) {
- dev_dbg(&pdev->dev, "No suitable DMA available\n");
+ if (etnaviv_of_dma_configure(dev))
return -ENODEV;
- }
-
- /*
- * Apply the same DMA configuration to the virtual etnaviv
- * device as the GPU we found. This assumes that all Vivante
- * GPUs in the system share the same DMA constraints.
- */
- if (first_node)
- of_dma_configure(&pdev->dev, first_node, true);
return component_master_add_with_match(dev, &etnaviv_master_ops, match);
}
--
2.25.1
