On Tue, May 16, 2023 at 5:27 AM Adam Ford <aford...@gmail.com> wrote: > > The DPHY timings are currently hard coded. Since the input > clock can be variable, the phy timings need to be variable > too. To facilitate this, we need to cache the hs_clock > based on what is generated from the PLL. > > The phy_mipi_dphy_get_default_config_for_hsclk function > configures the DPHY timings in pico-seconds, and a small macro > converts those timings into clock cycles based on the hs_clk. > > Signed-off-by: Adam Ford <aford...@gmail.com> > Signed-off-by: Lucas Stach <l.st...@pengutronix.de> > Tested-by: Chen-Yu Tsai <we...@chromium.org> > Tested-by: Frieder Schrempf <frieder.schre...@kontron.de> > Reviewed-by: Frieder Schrempf <frieder.schre...@kontron.de> > Tested-by: Michael Walle <mich...@walle.cc> > ---
Tested-by: Jagan Teki <ja...@amarulasolutions.com> # imx8mm-icore
