Dne petek, 05. maj 2023 ob 07:21:07 CEST je Roman Beranek napisal(a): > TCON0's source clock can be fed from either PLL_MIPI, or PLL_VIDEO0(2X), > however MIPI DSI output only seems to work when PLL_MIPI is selected and > thus the choice must be hardcoded in. > > Currently, this driver can't propagate rate change from N-K-M clocks > (such as PLL_MIPI) upwards. This prevents PLL_VIDEO0 from participating > in setting of the TCON0 data clock rate, limiting the precision with > which a target pixel clock can be matched. > > For outputs with fixed TCON0 divider, that is DSI and LVDS, the dotclock > can deviate up to 8% off target. > > Signed-off-by: Roman Beranek <m...@crly.cz>
Reviewed-by: Jernej Skrabec <jernej.skra...@gmail.com> Best regards, Jernej
