From: Matt Roper <matthew.d.ro...@intel.com>
Although we now sanitycheck MMIO access during driver load to make sure
the MMIO BAR isn't returning all 0xFFFFFFFF, there have been a few cases
where (temporarily?) unreliable MMIO access has happened after GPU
resets or power events. We'll often notice this on our next GT register
access since forcewake handling will fail; let's change our handling
slightly so that when this happens we print a more meaningful message
clarifying that the problem is the MMIO access, not forcewake
specifically.
Signed-off-by: Matt Roper <matthew.d.ro...@intel.com>
Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com>
Signed-off-by: Andi Shyti <andi.sh...@linux.intel.com>
---
drivers/gpu/drm/i915/intel_uncore.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 14ec45e6facfa..8b40a9772df5f 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -178,9 +178,15 @@ static inline void
fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d)
{
if (wait_ack_clear(d, FORCEWAKE_KERNEL)) {
- drm_err(&d->uncore->i915->drm,
- "%s: timed out waiting for forcewake ack to clear.\n",
- intel_uncore_forcewake_domain_to_str(d->id));
+ if (fw_ack(d) == ~0)
+ drm_err(&d->uncore->i915->drm,
+ "%s: MMIO unreliable (forcewake register
returns 0xFFFFFFFF)!\n",
+ intel_uncore_forcewake_domain_to_str(d->id));
+ else
+ drm_err(&d->uncore->i915->drm,
+ "%s: timed out waiting for forcewake ack to
clear.\n",
+ intel_uncore_forcewake_domain_to_str(d->id));
+
add_taint_for_CI(d->uncore->i915, TAINT_WARN); /* CI now
unreliable */
}
}
--
2.39.2
