On Sat, Dec 17, 2022 at 2:30 AM Liu Ying <victor....@nxp.com> wrote:
> On Fri, 2022-12-16 at 22:07 +0100, Lucas Stach wrote:
> > Add a simple wrapper driver for the DWC HDMI bridge driver that
> > implements the few bits that are necessary to abstract the i.MX8MP
> > SoC integration.
> >
> > Signed-off-by: Lucas Stach <l.st...@pengutronix.de>
> > Reviewed-by: Laurent Pinchart <laurent.pinch...@ideasonboard.com>
> > Tested-by: Marek Vasut <ma...@denx.de>
>
Tested-by: Adam Ford <aford...@gmail.com> #imx8mp-beacon
> > ---
> > drivers/gpu/drm/bridge/imx/Kconfig | 9 ++
> > drivers/gpu/drm/bridge/imx/Makefile | 2 +
> > drivers/gpu/drm/bridge/imx/imx8mp-hdmi.c | 140
> > +++++++++++++++++++++++
> > 3 files changed, 151 insertions(+)
> > create mode 100644 drivers/gpu/drm/bridge/imx/imx8mp-hdmi.c
> >
>
> Can you please provide a changelog since this is v2?
>
> > diff --git a/drivers/gpu/drm/bridge/imx/Kconfig
> > b/drivers/gpu/drm/bridge/imx/Kconfig
> > index 608f47f41bcd..d828d8bfd893 100644
> > --- a/drivers/gpu/drm/bridge/imx/Kconfig
> > +++ b/drivers/gpu/drm/bridge/imx/Kconfig
> > @@ -44,4 +44,13 @@ config DRM_IMX8QXP_PIXEL_LINK_TO_DPI
> > Choose this to enable pixel link to display pixel
> > interface(PXL2DPI)
> > found in Freescale i.MX8qxp processor.
> >
> > +config DRM_IMX8MP_DW_HDMI_BRIDGE
>
> Sort the config names alphabetically please.
>
> > + tristate "i.MX8MP HDMI bridge support"
>
> To show the prompts in this Kconfig file in a consistent fashion,
> please add 'Freescale' before 'i.MX8MP'.
>
> > + depends on OF
> > + depends on COMMON_CLK
> > + select DRM_DW_HDMI
> > + help
> > + Choose this to enable support for the internal HDMI encoder
> > found
> > + on the i.MX8MP SoC.
> > +
> > endif # ARCH_MXC || COMPILE_TEST
> > diff --git a/drivers/gpu/drm/bridge/imx/Makefile
> > b/drivers/gpu/drm/bridge/imx/Makefile
> > index aa90ec8d5433..03b0074ae538 100644
> > --- a/drivers/gpu/drm/bridge/imx/Makefile
> > +++ b/drivers/gpu/drm/bridge/imx/Makefile
> > @@ -7,3 +7,5 @@ obj-$(CONFIG_DRM_IMX8QXP_LDB) += imx8qxp-ldb.o
> > obj-$(CONFIG_DRM_IMX8QXP_PIXEL_COMBINER) += imx8qxp-pixel-combiner.o
> > obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK) += imx8qxp-pixel-link.o
> > obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI) += imx8qxp-pxl2dpi.o
> > +
> > +obj-$(CONFIG_DRM_IMX8MP_DW_HDMI_BRIDGE) += imx8mp-hdmi.o
>
> Sort the config names alphabetically.
>
> > diff --git a/drivers/gpu/drm/bridge/imx/imx8mp-hdmi.c
> > b/drivers/gpu/drm/bridge/imx/imx8mp-hdmi.c
> > new file mode 100644
> > index 000000000000..06849b817aed
> > --- /dev/null
> > +++ b/drivers/gpu/drm/bridge/imx/imx8mp-hdmi.c
> > @@ -0,0 +1,140 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +
> > +/*
> > + * Copyright (C) 2022 Pengutronix, Lucas Stach <
> > ker...@pengutronix.de>
> > + */
> > +
> > +#include <drm/bridge/dw_hdmi.h>
> > +#include <drm/drm_modes.h>
> > +#include <linux/clk.h>
> > +#include <linux/mod_devicetable.h>
> > +#include <linux/module.h>
> > +#include <linux/platform_device.h>
>
> Header files in linux/ come before those in drm/.
>
> > +
> > +struct imx8mp_hdmi {
> > + struct dw_hdmi_plat_data plat_data;
> > + struct dw_hdmi *dw_hdmi;
> > + struct clk *pixclk;
> > + struct clk *fdcc;
> > +};
> > +
> > +static enum drm_mode_status
> > +imx8mp_hdmi_mode_valid(struct dw_hdmi *dw_hdmi, void *data,
> > + const struct drm_display_info *info,
> > + const struct drm_display_mode *mode)
> > +{
> > + struct imx8mp_hdmi *hdmi = (struct imx8mp_hdmi *)data;
> > +
> > + if (mode->clock < 13500)
> > + return MODE_CLOCK_LOW;
> > +
> > + if (mode->clock > 297000)
> > + return MODE_CLOCK_HIGH;
> > +
> > + if (clk_round_rate(hdmi->pixclk, mode->clock * 1000) !=
> > + mode->clock * 1000)
> > + return MODE_CLOCK_RANGE;
> > +
> > + /* We don't support double-clocked and Interlaced modes */
> > + if ((mode->flags & DRM_MODE_FLAG_DBLCLK) ||
> > + (mode->flags & DRM_MODE_FLAG_INTERLACE))
> > + return MODE_BAD;
> > +
> > + return MODE_OK;
> > +}
> > +
> > +static int imx8mp_hdmi_phy_init(struct dw_hdmi *dw_hdmi, void *data,
> > + const struct drm_display_info *display,
> > + const struct drm_display_mode *mode)
> > +{
> > + return 0;
> > +}
> > +
> > +static void imx8mp_hdmi_phy_disable(struct dw_hdmi *dw_hdmi, void
> > *data)
> > +{
> > +}
> > +
> > +static void im8mp_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void
> > *data)
> > +{
> > + /*
> > + * Just release PHY core from reset, all other power management
> > is done
> > + * by the PHY driver.
> > + */
> > + dw_hdmi_phy_gen1_reset(hdmi);
> > +
> > + dw_hdmi_phy_setup_hpd(hdmi, data);
> > +}
> > +
> > +static const struct dw_hdmi_phy_ops imx8mp_hdmi_phy_ops = {
> > + .init = imx8mp_hdmi_phy_init,
> > + .disable = imx8mp_hdmi_phy_disable,
> > + .setup_hpd = im8mp_hdmi_phy_setup_hpd,
> > + .read_hpd = dw_hdmi_phy_read_hpd,
> > + .update_hpd = dw_hdmi_phy_update_hpd,
> > +};
> > +
> > +static int imx8mp_dw_hdmi_probe(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct dw_hdmi_plat_data *plat_data;
> > + struct imx8mp_hdmi *hdmi;
> > + int ret;
>
> Please fix this build warning:
>
> drivers/gpu/drm/bridge/imx/imx8mp-hdmi.c: In function
> ‘imx8mp_dw_hdmi_probe’:
> drivers/gpu/drm/bridge/imx/imx8mp-hdmi.c:80:13: warning: unused
> variable ‘ret’ [-Wunused-variable]
> 80 | int ret;
> | ^~~
>
> > +
> > + hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
> > + if (!hdmi)
> > + return -ENOMEM;
> > +
> > + plat_data = &hdmi->plat_data;
> > +
> > + hdmi->pixclk = devm_clk_get(dev, "pix");
> > + if (IS_ERR(hdmi->pixclk))
> > + return dev_err_probe(dev, PTR_ERR(hdmi->pixclk),
> > + "Unable to get pixel clock\n");
> > +
> > + hdmi->fdcc = devm_clk_get_enabled(dev, "fdcc");
> > + if (IS_ERR(hdmi->fdcc))
> > + return dev_err_probe(dev, PTR_ERR(hdmi->fdcc),
> > + "Unable to get FDCC clock\n");
>
> Similar to Laurent's comment on v1 here, why does fdcc clock need to be
> always enabled?
>
> > +
> > + plat_data->mode_valid = imx8mp_hdmi_mode_valid;
> > + plat_data->phy_ops = &imx8mp_hdmi_phy_ops;
> > + plat_data->phy_name = "SAMSUNG HDMI TX PHY";
> > + plat_data->priv_data = hdmi;
>
> Need to set plat_data->phy_force_vendor to be true? Or, you rely on
> reading the HDMI_CONFIG2_ID register to determine the phy type?
>
> > +
> > + hdmi->dw_hdmi = dw_hdmi_probe(pdev, plat_data);
> > + if (IS_ERR(hdmi->dw_hdmi))
> > + return PTR_ERR(hdmi->dw_hdmi);
> > +
> > + platform_set_drvdata(pdev, hdmi);
> > +
> > + return 0;
> > +}
> > +
> > +static int imx8mp_dw_hdmi_remove(struct platform_device *pdev)
> > +{
> > + struct imx8mp_hdmi *hdmi = platform_get_drvdata(pdev);
> > +
> > + dw_hdmi_remove(hdmi->dw_hdmi);
> > +
> > + return 0;
> > +}
> > +
> > +static const struct of_device_id imx8mp_dw_hdmi_of_table[] = {
> > + { .compatible = "fsl,imx8mp-hdmi" },
> > + { /* Sentinel */ },
>
> Nitpick: ',' after the sentinel is not needed since it's the last one.
>
> Regards,
> Liu Ying
>
> > +};
> > +MODULE_DEVICE_TABLE(of, imx8mp_dw_hdmi_of_table);
> > +
> > +static struct platform_driver imx8mp_dw_hdmi_platform_driver = {
> > + .probe = imx8mp_dw_hdmi_probe,
> > + .remove = imx8mp_dw_hdmi_remove,
> > + .driver = {
> > + .name = "imx8mp-dw-hdmi",
> > + .of_match_table = imx8mp_dw_hdmi_of_table,
> > + },
> > +};
> > +
> > +module_platform_driver(imx8mp_dw_hdmi_platform_driver);
> > +
> > +MODULE_DESCRIPTION("i.MX8MP HDMI encoder driver");
> > +MODULE_LICENSE("GPL");
>
>
