On 10/02/2023 12:34, Neil Armstrong wrote:
Switch the QMP PHY to the newly documented USB3/DP Combo PHY
bindings at [1] and add the DP controller nodes.
The DP output is shared with the USB3 SuperSpeed lanes and is
usually connected to an USB-C port which Altmode is controlled
by the PMIC Glink infrastructure in discution at [2] & [3].
DT changes tying the DP controller to the USB-C port on the HDK
boards will be sent later.
Bindings dependencies at [1]
[1]
https://lore.kernel.org/all/20230206-topic-sm8350-upstream-usb-dp-combo-phy-v1-1-ed849ae6b...@linaro.org/
[2]
https://lore.kernel.org/all/20230201041853.1934355-1-quic_bjora...@quicinc.com/
[3]
https://lore.kernel.org/all/20230130-topic-sm8450-upstream-pmic-glink-v1-0-0b0acfad3...@linaro.org/
Signed-off-by: Neil Armstrong <neil.armstr...@linaro.org>
Tested-by: Dmitry Baryshkov <dmitry.barysh...@linaro.org> #SM8350-HDK
--
With best wishes
Dmitry
