On Tue, Dec 13, 2022 at 03:41:19PM -0800, Matt Roper wrote:
> Programming of the ENABLE_PREFETCH_INTO_IC bit originally showed up in
> both the general DG2 tuning guide (applicable to all DG2
> variants/steppings) and under Wa_22012654132 (applicable only to
> specific steppings). It has now been removed from the tuning guide, and
> the guidance is to only program it in the specific steppings associated
> with the workaround.
>
> Bspec: 68331
Reviewed-by: Matt Atwood <matthew.s.atw...@intel.com>
> Signed-off-by: Matt Roper <matthew.d.ro...@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 27 ++++++++++-----------
> 1 file changed, 13 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 7d71f5bbddc8..bf84efb3f15f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -2913,20 +2913,6 @@ add_render_compute_tuning_settings(struct
> drm_i915_private *i915,
> if (IS_DG2(i915)) {
> wa_mcr_write_or(wal, XEHP_L3SCQREG7,
> BLEND_FILL_CACHING_OPT_DIS);
> wa_mcr_write_clr_set(wal, RT_CTRL, STACKID_CTRL,
> STACKID_CTRL_512);
> -
> - /*
> - * This is also listed as Wa_22012654132 for certain DG2
> - * steppings, but the tuning setting programming is a superset
> - * since it applies to all DG2 variants and steppings.
> - *
> - * Note that register 0xE420 is write-only and cannot be read
> - * back for verification on DG2 (due to Wa_14012342262), so
> - * we need to explicitly skip the readback.
> - */
> - wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0,
> - _MASKED_BIT_ENABLE(ENABLE_PREFETCH_INTO_IC),
> - 0 /* write-only, so skip validation */,
> - true);
> }
>
> /*
> @@ -3022,6 +3008,19 @@ general_render_compute_wa_init(struct intel_engine_cs
> *engine, struct i915_wa_li
> /* Wa_18017747507:dg2 */
> wa_masked_en(wal, VFG_PREEMPTION_CHICKEN,
> POLYGON_TRIFAN_LINELOOP_DISABLE);
> }
> +
> + if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_C0) ||
> IS_DG2_G11(i915))
> + /*
> + * Wa_22012654132
> + *
> + * Note that register 0xE420 is write-only and cannot be read
> + * back for verification on DG2 (due to Wa_14012342262), so
> + * we need to explicitly skip the readback.
> + */
> + wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0,
> + _MASKED_BIT_ENABLE(ENABLE_PREFETCH_INTO_IC),
> + 0 /* write-only, so skip validation */,
> + true);
> }
>
> static void
> --
> 2.38.1
>
