[PATCH v2] drm: lcdif: change burst size to 256B

[Marco Felsch]

If a axi bus master with a higher priority do a lot of memory access
FIFO underruns can be inspected. Increase the burst size to 256B to
avoid such underruns and to improve the memory access efficiency.

Fixes: 9db35bb349a0 ("drm: lcdif: Add support for i.MX8MP LCDIF variant")
Signed-off-by: Marco Felsch <m.fel...@pengutronix.de>
---
Changelog:

v2:
- added fixes tag

 drivers/gpu/drm/mxsfb/lcdif_kms.c  | 14 ++++++++++++--
 drivers/gpu/drm/mxsfb/lcdif_regs.h |  4 ++++
 2 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/mxsfb/lcdif_kms.c 
b/drivers/gpu/drm/mxsfb/lcdif_kms.c
index b1092aab1423..2a90c24df297 100644
--- a/drivers/gpu/drm/mxsfb/lcdif_kms.c
+++ b/drivers/gpu/drm/mxsfb/lcdif_kms.c
@@ -142,8 +142,18 @@ static void lcdif_set_mode(struct lcdif_drm_private 
*lcdif, u32 bus_flags)
               CTRLDESCL0_1_WIDTH(m->hdisplay),
               lcdif->base + LCDC_V8_CTRLDESCL0_1);
 
-       writel(CTRLDESCL0_3_PITCH(lcdif->crtc.primary->state->fb->pitches[0]),
-              lcdif->base + LCDC_V8_CTRLDESCL0_3);
+       /*
+        * Undocumented P_SIZE and T_SIZE register but those written in the
+        * downstream kernel those registers control the AXI burst size. As of
+        * now there are two known values:
+        *  1 - 128Byte
+        *  2 - 256Byte
+        * Downstream set it to 256B burst size to improve the memory
+        * efficiency so set it here too.
+        */
+       ctrl = CTRLDESCL0_3_P_SIZE(2) | CTRLDESCL0_3_T_SIZE(2) |
+              CTRLDESCL0_3_PITCH(lcdif->crtc.primary->state->fb->pitches[0]);
+       writel(ctrl, lcdif->base + LCDC_V8_CTRLDESCL0_3);
 }
 
 static void lcdif_enable_controller(struct lcdif_drm_private *lcdif)
diff --git a/drivers/gpu/drm/mxsfb/lcdif_regs.h 
b/drivers/gpu/drm/mxsfb/lcdif_regs.h
index c70220651e3a..8e8bef175bf2 100644
--- a/drivers/gpu/drm/mxsfb/lcdif_regs.h
+++ b/drivers/gpu/drm/mxsfb/lcdif_regs.h
@@ -190,6 +190,10 @@
 #define CTRLDESCL0_1_WIDTH(n)          ((n) & 0xffff)
 #define CTRLDESCL0_1_WIDTH_MASK                GENMASK(15, 0)
 
+#define CTRLDESCL0_3_P_SIZE(n)         (((n) << 20) & CTRLDESCL0_3_P_SIZE_MASK)
+#define CTRLDESCL0_3_P_SIZE_MASK       GENMASK(22, 20)
+#define CTRLDESCL0_3_T_SIZE(n)         (((n) << 16) & CTRLDESCL0_3_T_SIZE_MASK)
+#define CTRLDESCL0_3_T_SIZE_MASK       GENMASK(17, 16)
 #define CTRLDESCL0_3_PITCH(n)          ((n) & 0xffff)
 #define CTRLDESCL0_3_PITCH_MASK                GENMASK(15, 0)
 
-- 
2.30.2