On Tue, Oct 18, 2022 at 10:20:40PM -0700, Ashutosh Dixit wrote:
> From: Don Hiatt <don.hi...@intel.com>
>
> On GEN12+ use GEN12_RPSTAT register to get actual resolved GT
> freq. GEN12_RPSTAT does not require a forcewake and will return 0 freq if
> GT is in RC6.
>
> v2:
> - Fixed review comments(Ashutosh)
> - Added function intel_rps_read_rpstat_fw to read RPSTAT without
> forcewake, required especially for GEN6_RPSTAT1 (Ashutosh, Tvrtko)
> v3:
> - Updated commit title and message for more clarity (Ashutosh)
> - Replaced intel_rps_read_rpstat with direct read to GEN12_RPSTAT1 in
> read_cagf (Ashutosh)
>
> Cc: Don Hiatt <donhi...@gmail.com>
> Cc: Andi Shyti <andi.sh...@intel.com>
> Signed-off-by: Don Hiatt <don.hi...@intel.com>
> Signed-off-by: Badal Nilawar <badal.nila...@intel.com>
> Signed-off-by: Ashutosh Dixit <ashutosh.di...@intel.com>
> Reviewed-by: Andi Shyti <andi.sh...@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 2 ++
> drivers/gpu/drm/i915/gt/intel_rps.c | 32 +++++++++++++++++++++----
> drivers/gpu/drm/i915/gt/intel_rps.h | 2 ++
> drivers/gpu/drm/i915/i915_pmu.c | 3 +--
> 4 files changed, 33 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 36d95b79022c0..a7a0129d0e3fc 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -1543,6 +1543,8 @@
>
> #define GEN12_RPSTAT1 _MMIO(0x1381b4)
> #define GEN12_VOLTAGE_MASK REG_GENMASK(10, 0)
> +#define GEN12_CAGF_SHIFT 11
we don't need to define the shift if we use the REG_FIELD_GET
> +#define GEN12_CAGF_MASK REG_GENMASK(19, 11)
ah, cool, this is already right and in place
(ignore my comment about this in the other patch)
>
> #define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4))
> #define GEN11_CSME (31)
> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
> b/drivers/gpu/drm/i915/gt/intel_rps.c
> index fc23c562d9b2a..df21258976d86 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> @@ -2068,12 +2068,34 @@ void intel_rps_sanitize(struct intel_rps *rps)
> rps_disable_interrupts(rps);
> }
>
> +u32 intel_rps_read_rpstat_fw(struct intel_rps *rps)
> +{
> + struct drm_i915_private *i915 = rps_to_i915(rps);
> + i915_reg_t rpstat;
> +
> + rpstat = (GRAPHICS_VER(i915) >= 12) ? GEN12_RPSTAT1 : GEN6_RPSTAT1;
> +
> + return intel_uncore_read_fw(rps_to_gt(rps)->uncore, rpstat);
> +}
> +
> +u32 intel_rps_read_rpstat(struct intel_rps *rps)
> +{
> + struct drm_i915_private *i915 = rps_to_i915(rps);
> + i915_reg_t rpstat;
> +
> + rpstat = (GRAPHICS_VER(i915) >= 12) ? GEN12_RPSTAT1 : GEN6_RPSTAT1;
> +
> + return intel_uncore_read(rps_to_gt(rps)->uncore, rpstat);
> +}
> +
> u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat)
> {
> struct drm_i915_private *i915 = rps_to_i915(rps);
> u32 cagf;
>
> - if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
> + if (GRAPHICS_VER(i915) >= 12)
> + cagf = (rpstat & GEN12_CAGF_MASK) >> GEN12_CAGF_SHIFT;
cagf = REG_FIELD_GET(GEN12_CAGF_MASK, rpstat);
> + else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
> cagf = (rpstat >> 8) & 0xff;
> else if (GRAPHICS_VER(i915) >= 9)
> cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
> @@ -2094,7 +2116,9 @@ static u32 read_cagf(struct intel_rps *rps)
> struct intel_uncore *uncore = rps_to_uncore(rps);
> u32 freq;
>
> - if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
> + if (GRAPHICS_VER(i915) >= 12) {
> + freq = intel_uncore_read(uncore, GEN12_RPSTAT1);
> + } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
> vlv_punit_get(i915);
> freq = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
> vlv_punit_put(i915);
> @@ -2260,7 +2284,7 @@ static void rps_frequency_dump(struct intel_rps *rps,
> struct drm_printer *p)
> rpinclimit = intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD);
> rpdeclimit = intel_uncore_read(uncore, GEN6_RP_DOWN_THRESHOLD);
>
> - rpstat = intel_uncore_read(uncore, GEN6_RPSTAT1);
> + rpstat = intel_rps_read_rpstat(rps);
> rpcurupei = intel_uncore_read(uncore, GEN6_RP_CUR_UP_EI) &
> GEN6_CURICONT_MASK;
> rpcurup = intel_uncore_read(uncore, GEN6_RP_CUR_UP) &
> GEN6_CURBSYTAVG_MASK;
> rpprevup = intel_uncore_read(uncore, GEN6_RP_PREV_UP) &
> GEN6_CURBSYTAVG_MASK;
> @@ -2395,7 +2419,7 @@ static void slpc_frequency_dump(struct intel_rps *rps,
> struct drm_printer *p)
> drm_printf(p, "PM MASK=0x%08x\n", pm_mask);
> drm_printf(p, "pm_intrmsk_mbz: 0x%08x\n",
> rps->pm_intrmsk_mbz);
> - drm_printf(p, "RPSTAT1: 0x%08x\n", intel_uncore_read(uncore,
> GEN6_RPSTAT1));
> + drm_printf(p, "RPSTAT1: 0x%08x\n", intel_rps_read_rpstat(rps));
> drm_printf(p, "RPNSWREQ: %dMHz\n",
> intel_rps_get_requested_frequency(rps));
> drm_printf(p, "Lowest (RPN) frequency: %dMHz\n",
> intel_gpu_freq(rps, caps.min_freq));
> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.h
> b/drivers/gpu/drm/i915/gt/intel_rps.h
> index 110300dfd4383..9e1cad9ba0e9c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rps.h
> +++ b/drivers/gpu/drm/i915/gt/intel_rps.h
> @@ -48,6 +48,8 @@ u32 intel_rps_get_rp1_frequency(struct intel_rps *rps);
> u32 intel_rps_get_rpn_frequency(struct intel_rps *rps);
> u32 intel_rps_read_punit_req(struct intel_rps *rps);
> u32 intel_rps_read_punit_req_frequency(struct intel_rps *rps);
> +u32 intel_rps_read_rpstat(struct intel_rps *rps);
> +u32 intel_rps_read_rpstat_fw(struct intel_rps *rps);
> void gen6_rps_get_freq_caps(struct intel_rps *rps, struct
> intel_rps_freq_caps *caps);
> void intel_rps_raise_unslice(struct intel_rps *rps);
> void intel_rps_lower_unslice(struct intel_rps *rps);
> diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
> index 958b37123bf12..67140a87182f8 100644
> --- a/drivers/gpu/drm/i915/i915_pmu.c
> +++ b/drivers/gpu/drm/i915/i915_pmu.c
> @@ -371,7 +371,6 @@ static void
> frequency_sample(struct intel_gt *gt, unsigned int period_ns)
> {
> struct drm_i915_private *i915 = gt->i915;
> - struct intel_uncore *uncore = gt->uncore;
> struct i915_pmu *pmu = &i915->pmu;
> struct intel_rps *rps = >->rps;
>
> @@ -394,7 +393,7 @@ frequency_sample(struct intel_gt *gt, unsigned int
> period_ns)
> * case we assume the system is running at the intended
> * frequency. Fortunately, the read should rarely fail!
> */
> - val = intel_uncore_read_fw(uncore, GEN6_RPSTAT1);
> + val = intel_rps_read_rpstat_fw(rps);
> if (val)
> val = intel_rps_get_cagf(rps, val);
> else
> --
> 2.38.0
>
