Avoid the array lookup, converting the PLL macros after ICL to
_PICK_EVEN_RANGES. This provides the following reduction in code size:
$ size build64/drivers/gpu/drm/i915/i915.o{.old,.new}
text data bss dec hex filename
3570297 131232 6824 3708353 3895c1
build64/drivers/gpu/drm/i915/i915.o.old
3569686 131232 6824 3707742 38935e
build64/drivers/gpu/drm/i915/i915.o.new
At the same time it's safer, avoiding out-of-bounds array access.
Signed-off-by: Lucas De Marchi <lucas.demar...@intel.com>
(cherry picked from commit 592d15e3d72009bfb9f7a933c292510f8564a4cf)
---
drivers/gpu/drm/i915/i915_reg.h | 59 ++++++++++++++++++++---------------------
1 file changed, 29 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ad8f839046f5..df30bcc53489 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7313,13 +7313,15 @@ enum skl_power_gate {
#define PLL_LOCK REG_BIT(30)
#define PLL_POWER_ENABLE REG_BIT(27)
#define PLL_POWER_STATE REG_BIT(26)
-#define ICL_DPLL_ENABLE(pll) _MMIO_PLL3(pll, _DPLL0_ENABLE, _DPLL1_ENABLE, \
- _ADLS_DPLL2_ENABLE,
_ADLS_DPLL3_ENABLE)
+#define ICL_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_RANGES(pll, (pll) < 3,
\
+ _DPLL0_ENABLE,
_DPLL1_ENABLE, \
+ _ADLS_DPLL3_ENABLE,
_ADLS_DPLL3_ENABLE))
#define _DG2_PLL3_ENABLE 0x4601C
-#define DG2_PLL_ENABLE(pll) _MMIO_PLL3(pll, _DPLL0_ENABLE, _DPLL1_ENABLE, \
- _ADLS_DPLL2_ENABLE, _DG2_PLL3_ENABLE)
+#define DG2_PLL_ENABLE(pll) _MMIO(_PICK_EVEN_RANGES(pll, (pll) < 3,
\
+ _DPLL0_ENABLE,
_DPLL1_ENABLE, \
+ _DG2_PLL3_ENABLE,
_DG2_PLL3_ENABLE))
#define TBT_PLL_ENABLE _MMIO(0x46020)
@@ -7332,8 +7334,9 @@ enum skl_power_gate {
_MG_PLL2_ENABLE)
/* DG1 PLL */
-#define DG1_DPLL_ENABLE(pll) _MMIO_PLL3(pll, _DPLL0_ENABLE, _DPLL1_ENABLE, \
- _MG_PLL1_ENABLE, _MG_PLL2_ENABLE)
+#define DG1_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_RANGES(pll, (pll) < 2,
\
+ _DPLL0_ENABLE,
_DPLL1_ENABLE, \
+ _MG_PLL1_ENABLE,
_MG_PLL2_ENABLE))
/* ADL-P Type C PLL */
#define PORTTC1_PLL_ENABLE 0x46038
@@ -7393,9 +7396,9 @@ enum skl_power_gate {
#define _TGL_DPLL0_CFGCR0 0x164284
#define _TGL_DPLL1_CFGCR0 0x16428C
#define _TGL_TBTPLL_CFGCR0 0x16429C
-#define TGL_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
- _TGL_DPLL1_CFGCR0, \
- _TGL_TBTPLL_CFGCR0)
+#define TGL_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_RANGES(pll, (pll) < 2,
\
+ _TGL_DPLL0_CFGCR0,
_TGL_DPLL1_CFGCR0, \
+ _TGL_TBTPLL_CFGCR0,
_TGL_TBTPLL_CFGCR0))
#define RKL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR0, \
_TGL_DPLL1_CFGCR0)
@@ -7408,40 +7411,36 @@ enum skl_power_gate {
#define _TGL_DPLL0_CFGCR1 0x164288
#define _TGL_DPLL1_CFGCR1 0x164290
#define _TGL_TBTPLL_CFGCR1 0x1642A0
-#define TGL_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
- _TGL_DPLL1_CFGCR1, \
- _TGL_TBTPLL_CFGCR1)
+#define TGL_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_RANGES(pll, (pll) < 2,
\
+ _TGL_DPLL0_CFGCR1,
_TGL_DPLL1_CFGCR1, \
+ _TGL_TBTPLL_CFGCR1,
_TGL_TBTPLL_CFGCR1))
#define RKL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, \
_TGL_DPLL1_CFGCR1)
#define _DG1_DPLL2_CFGCR0 0x16C284
#define _DG1_DPLL3_CFGCR0 0x16C28C
-#define DG1_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
- _TGL_DPLL1_CFGCR0, \
- _DG1_DPLL2_CFGCR0, \
- _DG1_DPLL3_CFGCR0)
+#define DG1_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_RANGES(pll, (pll) < 2,
\
+ _TGL_DPLL0_CFGCR0,
_TGL_DPLL1_CFGCR0, \
+ _DG1_DPLL2_CFGCR0,
_DG1_DPLL3_CFGCR0))
#define _DG1_DPLL2_CFGCR1 0x16C288
#define _DG1_DPLL3_CFGCR1 0x16C290
-#define DG1_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
- _TGL_DPLL1_CFGCR1, \
- _DG1_DPLL2_CFGCR1, \
- _DG1_DPLL3_CFGCR1)
+#define DG1_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_RANGES(pll, (pll) <
2, \
+ _TGL_DPLL0_CFGCR1,
_TGL_DPLL1_CFGCR1, \
+ _DG1_DPLL2_CFGCR1,
_DG1_DPLL3_CFGCR1))
/* For ADL-S DPLL4_CFGCR0/1 are used to control DPLL2 */
-#define _ADLS_DPLL3_CFGCR0 0x1642C0
#define _ADLS_DPLL4_CFGCR0 0x164294
-#define ADLS_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
- _TGL_DPLL1_CFGCR0, \
- _ADLS_DPLL4_CFGCR0, \
- _ADLS_DPLL3_CFGCR0)
+#define _ADLS_DPLL3_CFGCR0 0x1642C0
+#define ADLS_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_RANGES(pll, (pll) < 2,
\
+ _TGL_DPLL0_CFGCR0,
_TGL_DPLL1_CFGCR0, \
+ _ADLS_DPLL4_CFGCR0,
_ADLS_DPLL3_CFGCR0))
-#define _ADLS_DPLL3_CFGCR1 0x1642C4
#define _ADLS_DPLL4_CFGCR1 0x164298
-#define ADLS_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
- _TGL_DPLL1_CFGCR1, \
- _ADLS_DPLL4_CFGCR1, \
- _ADLS_DPLL3_CFGCR1)
+#define _ADLS_DPLL3_CFGCR1 0x1642C4
+#define ADLS_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_RANGES(pll, (pll) < 2,
\
+ _TGL_DPLL0_CFGCR1,
_TGL_DPLL1_CFGCR1, \
+ _ADLS_DPLL4_CFGCR1,
_ADLS_DPLL3_CFGCR1))
#define _DKL_PHY1_BASE 0x168000
#define _DKL_PHY2_BASE 0x169000
--
b4 0.10.1
