On 7/26/22 11:43, Marco Felsch wrote:
FIFO underruns are seen if a AXI bus master with a higher priority do a
lot of memory access. Increase the burst size to 256B to avoid such
underruns and to improve the memory access efficiency.
Sigh, this again ...
diff --git a/drivers/gpu/drm/mxsfb/lcdif_kms.c
b/drivers/gpu/drm/mxsfb/lcdif_kms.c
index 1bec1279c8b5..1f22ea5896d5 100644
--- a/drivers/gpu/drm/mxsfb/lcdif_kms.c
+++ b/drivers/gpu/drm/mxsfb/lcdif_kms.c
@@ -143,8 +143,20 @@ static void lcdif_set_mode(struct lcdif_drm_private
*lcdif, u32 bus_flags)
CTRLDESCL0_1_WIDTH(m->crtc_hdisplay),
lcdif->base + LCDC_V8_CTRLDESCL0_1);
- writel(CTRLDESCL0_3_PITCH(lcdif->crtc.primary->state->fb->pitches[0]),
- lcdif->base + LCDC_V8_CTRLDESCL0_3);
+ /*
+ * Undocumented P_SIZE and T_SIZE bit fields but according the
+ * downstream kernel they control the AXI burst size. As of now there
+ * are two known values:
+ * 1 - 128Byte
+ * 2 - 256Byte
+ *
+ * Downstream has set the burst size to 256Byte to improve the memory
+ * efficiency so set it here too. This also reduces the FIFO underrun
+ * possibility.
+ */
+ ctrl = CTRLDESCL0_3_P_SIZE(2) | CTRLDESCL0_3_T_SIZE(2) |
+ CTRLDESCL0_3_PITCH(lcdif->crtc.primary->state->fb->pitches[0]);
+ writel(ctrl, lcdif->base + LCDC_V8_CTRLDESCL0_3);
}
Sometimes I wonder whether this might be some successor of MXSFB
LCDIF_CTRL2n OUTSTANDING_REQS and BURST_LEN_B fields.
+CC Liu, who seems to have a lot of knowledge about this IP.
Reviewed-by: Marek Vasut <ma...@denx.de>
