On 7/6/22 15:28, Lucas Stach wrote:
The current CLRSIPO count is marginal and does not work with high DSI clock rates. Increase it a bit to allow the DSI link to work at up to 1Gbps lane speed.Signed-off-by: Lucas Stach <l.st...@pengutronix.de>
Reviewed-by: Marek Vasut <ma...@denx.de> Tested-by: Marek Vasut <ma...@denx.de>
