On 7/6/22 15:28, Lucas Stach wrote:
Disable the main link PHYs and put them into reset when the main link is disabled. When the PHYs stay enabled while the rest of the DP link circuits are disabled there is some noise on the data lanes, which some displays try to lock onto, waking them up from their low power state.Signed-off-by: Lucas Stach <l.st...@pengutronix.de>
Reviewed-by: Marek Vasut <ma...@denx.de> Tested-by: Marek Vasut <ma...@denx.de>
