Reviewed-by: Vinay Simha BN <simha...@gmail.com> On Thu, Jun 16, 2022 at 3:55 AM Jiri Vanek <jirivan...@gmail.com> wrote:
> Use the same PCLK divide option (divide DSI clock to generate pixel clock) > which is set to LVDS Configuration Register (LVCFG) also for a VSync delay > calculation. Without this change an auxiliary variable could underflow > during the calculation for some dual-link LVDS panels and then calculated > VSync delay is wrong. This leads to a shifted picture on a panel. > > Tested-by: Jiri Vanek <jirivan...@gmail.com> > Signed-off-by: Jiri Vanek <jirivan...@gmail.com> > --- > drivers/gpu/drm/bridge/tc358775.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/bridge/tc358775.c > b/drivers/gpu/drm/bridge/tc358775.c > index cd2721ab02a9..fecb8558b49a 100644 > --- a/drivers/gpu/drm/bridge/tc358775.c > +++ b/drivers/gpu/drm/bridge/tc358775.c > @@ -430,7 +430,7 @@ static void tc_bridge_enable(struct drm_bridge *bridge) > val = TC358775_VPCTRL_MSF(1); > > dsiclk = mode->crtc_clock * 3 * tc->bpc / tc->num_dsi_lanes / 1000; > - clkdiv = dsiclk / DIVIDE_BY_3 * tc->lvds_link; > + clkdiv = dsiclk / (tc->lvds_link == DUAL_LINK ? DIVIDE_BY_6 : > DIVIDE_BY_3); > byteclk = dsiclk / 4; > t1 = hactive * (tc->bpc * 3 / 8) / tc->num_dsi_lanes; > t2 = ((100000 / clkdiv)) * (hactive + hback_porch + hsync_len + > hfront_porch) / 1000; > -- > 2.30.2 > > -- regards, vinaysimha
