Tvrtko Ursulin <tvrtko.ursu...@linux.intel.com> writes: > From: Tvrtko Ursulin <tvrtko.ursu...@intel.com> > > DRM_DEBUG_WARN_ON should only be used when we are certain CI is guaranteed > to exercise a certain code path, so in case of values coming from MMIO > reads we cannot be sure CI will have all the possible SKUs and parts, or > that it will catch all possible error conditions. Use drm_warn instead. > > Signed-off-by: Tvrtko Ursulin <tvrtko.ursu...@intel.com> > Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com> > Cc: Jani Nikula <jani.nik...@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuopp...@linux.intel.com> > --- > drivers/gpu/drm/i915/gt/intel_ring_submission.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c > b/drivers/gpu/drm/i915/gt/intel_ring_submission.c > index 5423bfd301ad..f8f279a195c0 100644 > --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c > +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c > @@ -117,7 +117,9 @@ static void flush_cs_tlb(struct intel_engine_cs *engine) > return; > > /* ring should be idle before issuing a sync flush*/ > - GEM_DEBUG_WARN_ON((ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0); > + if ((ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0) > + drm_warn(&engine->i915->drm, "%s not idle before sync flush!\n", > + engine->name); > > ENGINE_WRITE_FW(engine, RING_INSTPM, > _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | > -- > 2.32.0
