On Tue, Mar 01, 2022 at 03:15:49PM -0800, Matt Roper wrote:
> From: Srinivasan Shanmugam <srinivasa...@intel.com>
>
> Registers that exist in the shared render/compute reset domain need to
> be placed on an engine workaround list to ensure that they are properly
> re-applied whenever an RCS or CCS engine is reset. We have a number of
> workarounds (updating registers MLTICTXCTL, L3SQCREG1_CCS0,
> GEN12_MERT_MOD_CTRL, and GEN12_GAMCNTRL_CTRL) that are incorrectly
> implemented on the 'gt' workaround list and need to be moved
> accordingly.
>
> Cc: Matt Roper <matthew.d.ro...@intel.com>
> Signed-off-by: Srinivasan Shanmugam <srinivasa...@intel.com>
> Signed-off-by: Matt Roper <matthew.d.ro...@intel.com>
Reviewed-by: Matt Roper <matthew.d.ro...@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 26 ++++++++++-----------
> 1 file changed, 13 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 0b9435d62808..c014b40d2e9f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1343,12 +1343,6 @@ xehpsdv_gt_workarounds_init(struct intel_gt *gt,
> struct i915_wa_list *wal)
> /* Wa_1409757795:xehpsdv */
> wa_write_or(wal, SCCGCTL94DC, CG3DDISURB);
>
> - /* Wa_18011725039:xehpsdv */
> - if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A1, STEP_B0)) {
> - wa_masked_dis(wal, MLTICTXCTL, TDONRENDER);
> - wa_write_or(wal, L3SQCREG1_CCS0, FLUSHALLNONCOH);
> - }
> -
> /* Wa_16011155590:xehpsdv */
> if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
> wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE,
> @@ -1385,19 +1379,12 @@ xehpsdv_gt_workarounds_init(struct intel_gt *gt,
> struct i915_wa_list *wal)
> GAMTLBVEBOX0_CLKGATE_DIS);
> }
>
> - /* Wa_14012362059:xehpsdv */
> - wa_write_or(wal, GEN12_MERT_MOD_CTRL, FORCE_MISS_FTLB);
> -
> /* Wa_16012725990:xehpsdv */
> if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A1, STEP_FOREVER))
> wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE,
> VFUNIT_CLKGATE_DIS);
>
> /* Wa_14011060649:xehpsdv */
> wa_14011060649(gt, wal);
> -
> - /* Wa_14014368820:xehpsdv */
> - wa_write_or(wal, GEN12_GAMCNTRL_CTRL, INVALIDATION_BROADCAST_MODE_DIS |
> - GLOBAL_INVALIDATION_MODE);
> }
>
> static void
> @@ -2617,6 +2604,19 @@ general_render_compute_wa_init(struct intel_engine_cs
> *engine, struct i915_wa_li
> /* Wa_14010449647:xehpsdv */
> wa_masked_en(wal, GEN7_HALF_SLICE_CHICKEN1,
> GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
> +
> + /* Wa_18011725039:xehpsdv */
> + if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A1, STEP_B0)) {
> + wa_masked_dis(wal, MLTICTXCTL, TDONRENDER);
> + wa_write_or(wal, L3SQCREG1_CCS0, FLUSHALLNONCOH);
> + }
> +
> + /* Wa_14012362059:xehpsdv */
> + wa_write_or(wal, GEN12_MERT_MOD_CTRL, FORCE_MISS_FTLB);
> +
> + /* Wa_14014368820:xehpsdv */
> + wa_write_or(wal, GEN12_GAMCNTRL_CTRL,
> INVALIDATION_BROADCAST_MODE_DIS |
> + GLOBAL_INVALIDATION_MODE);
> }
> }
>
> --
> 2.34.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
