On Thu, Feb 10, 2022 at 10:36:34AM -0800, Michael Cheng wrote:
> Use drm_clflush_virt_range instead of directly invoking clflush. This
> will prevent compiler errors when building for non-x86 architectures.
>
> v2(Michael Cheng): Remove extra clflush
>
> v3(Michael Cheng): Remove memory barrier since drm_clflush_virt_range
> takes care of it.
>
> Signed-off-by: Michael Cheng <michael.ch...@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 5 ++---
> 1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index 6186a5e4b191..11b864fd68a5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -2945,9 +2945,8 @@ reset_csb(struct intel_engine_cs *engine, struct
> i915_request **inactive)
> {
> struct intel_engine_execlists * const execlists = &engine->execlists;
>
> - mb(); /* paranoia: read the CSB pointers from after the reset */
> - clflush(execlists->csb_write);
> - mb();
> + drm_clflush_virt_range(execlists->csb_write,
> + sizeof(execlists->csb_write));
I think you technically want sizeof(execlists->csb_write[0]) here,
right? I.e., the size of the value (32-bits), not the size of the
pointer (32 or 64 depending on architecture). Not that it will really
change the behavior since it all works out to a single cacheline in the
end.
Aside from that,
Reviewed-by: Matt Roper <matthew.d.ro...@intel.com>
>
> inactive = process_csb(engine, inactive); /* drain preemption events */
>
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
