On 11/02/2022 20:27, alyssa.rosenzw...@collabora.com wrote:
> From: Alyssa Rosenzweig <alyssa.rosenzw...@collabora.com>
>
> Add handling for the HW_ISSUE_TTRX_2968_TTRX_3162 quirk. Logic ported
> from kbase. kbase lists this workaround as used on Mali-G57.
>
> Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzw...@collabora.com>
Reviewed-by: Steven Price <steven.pr...@arm.com>
> ---
> drivers/gpu/drm/panfrost/panfrost_gpu.c | 3 +++
> drivers/gpu/drm/panfrost/panfrost_issues.h | 3 +++
> drivers/gpu/drm/panfrost/panfrost_regs.h | 1 +
> 3 files changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/panfrost/panfrost_gpu.c
> b/drivers/gpu/drm/panfrost/panfrost_gpu.c
> index 50c8922694d7..1c1e2017aa80 100644
> --- a/drivers/gpu/drm/panfrost/panfrost_gpu.c
> +++ b/drivers/gpu/drm/panfrost/panfrost_gpu.c
> @@ -108,6 +108,9 @@ static void panfrost_gpu_init_quirks(struct
> panfrost_device *pfdev)
> quirks |= SC_LS_ALLOW_ATTR_TYPES;
> }
>
> + if (panfrost_has_hw_issue(pfdev, HW_ISSUE_TTRX_2968_TTRX_3162))
> + quirks |= SC_VAR_ALGORITHM;
> +
> if (panfrost_has_hw_feature(pfdev, HW_FEATURE_TLS_HASHING))
> quirks |= SC_TLS_HASH_ENABLE;
>
> diff --git a/drivers/gpu/drm/panfrost/panfrost_issues.h
> b/drivers/gpu/drm/panfrost/panfrost_issues.h
> index 8e59d765bf19..3af7d723377e 100644
> --- a/drivers/gpu/drm/panfrost/panfrost_issues.h
> +++ b/drivers/gpu/drm/panfrost/panfrost_issues.h
> @@ -125,6 +125,9 @@ enum panfrost_hw_issue {
> * kernel must fiddle with L2 caches to prevent data leakage */
> HW_ISSUE_TGOX_R1_1234,
>
> + /* Must set SC_VAR_ALGORITHM */
> + HW_ISSUE_TTRX_2968_TTRX_3162,
> +
> HW_ISSUE_END
> };
>
> diff --git a/drivers/gpu/drm/panfrost/panfrost_regs.h
> b/drivers/gpu/drm/panfrost/panfrost_regs.h
> index 16e776cc82ea..fa1e1af56e17 100644
> --- a/drivers/gpu/drm/panfrost/panfrost_regs.h
> +++ b/drivers/gpu/drm/panfrost/panfrost_regs.h
> @@ -195,6 +195,7 @@
> #define SC_TLS_HASH_ENABLE BIT(17)
> #define SC_LS_ATTR_CHECK_DISABLE BIT(18)
> #define SC_ENABLE_TEXGRD_FLAGS BIT(25)
> +#define SC_VAR_ALGORITHM BIT(29)
> /* End SHADER_CONFIG register */
>
> /* TILER_CONFIG register */
