MSO will require segment pixel overlap information from the
EDID. Postpone MSO init until after we've read and cached the EDID.

Signed-off-by: Jani Nikula <jani.nik...@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index 7f8e8865048f..8e75543334c2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2575,8 +2575,6 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
         */
        intel_edp_init_source_oui(intel_dp, true);
 
-       intel_edp_mso_init(intel_dp);
-
        return true;
 }
 
@@ -5269,6 +5267,9 @@ static bool intel_edp_init_connector(struct intel_dp 
*intel_dp,
        if (fixed_mode)
                downclock_mode = intel_dp_drrs_init(intel_connector, 
fixed_mode);
 
+       /* MSO requires information from the EDID */
+       intel_edp_mso_init(intel_dp);
+
        /* multiply the mode clock and horizontal timings for MSO */
        intel_edp_mso_mode_fixup(intel_connector, fixed_mode);
        intel_edp_mso_mode_fixup(intel_connector, downclock_mode);
-- 
2.20.1

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