Hi Am 09.07.21 um 20:53 schrieb Sam Ravnborg:
On Mon, Jul 05, 2021 at 02:45:05PM +0200, Thomas Zimmermann wrote:Return -EINVAL if there's no PLL configuration for the given pixel clock.Signed-off-by: Thomas Zimmermann <tzimmerm...@suse.de> --- drivers/gpu/drm/mgag200/mgag200_mode.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mgag200/mgag200_mode.c b/drivers/gpu/drm/mgag200/mgag200_mode.c index 482843ebb69f..045a20055515 100644 --- a/drivers/gpu/drm/mgag200/mgag200_mode.c +++ b/drivers/gpu/drm/mgag200/mgag200_mode.c @@ -134,7 +134,7 @@ static int mgag200_g200_set_plls(struct mga_device *mdev, long clock)if (clock > p_clk_max) {drm_err(dev, "Pixel Clock %ld too high\n", clock); - return 1; + return -EINVAL; }if (clock < p_clk_min >> 3)@@ -293,7 +293,7 @@ static int mga_g200se_set_plls(struct mga_device *mdev, long clock)if (delta > permitteddelta) {pr_warn("PLL delta too large\n"); - return 1; + return -EINVAL; }misc = RREG8(MGA_MISC_IN);The return value is ignored but I assume it makes sense in a later patch. Should mgag200_crtc_set_plls() return -EINVAL if there was no match? Today it returns 0 - which is not an error.
Indeed. Patch 12 moves some of this functionality into the atomic check, where it will be tested for success.
Not handling the type in the switch is actually a driver bug. I'll see if I can add a rsp error in one of the patches.
Best regards Thomas
Sam
-- Thomas Zimmermann Graphics Driver Developer SUSE Software Solutions Germany GmbH Maxfeldstr. 5, 90409 Nürnberg, Germany (HRB 36809, AG Nürnberg) Geschäftsführer: Felix Imendörffer
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