The check on unchanged HS clock rate in ->mode_set() improves
the callback's performance a bit by early return. However,
the up-coming patch would get MIPI DSI controller and PHY ready
in ->mode_set() after that check, thus likely skipped.
So, this patch removes that check to make sure MIPI DSI controller
and PHY will be brought up and taken down from ->mode_set() and
->atomic_disable() respectively in pairs.
Cc: Andrzej Hajda <a.ha...@samsung.com>
Cc: Neil Armstrong <narmstr...@baylibre.com>
Cc: Robert Foss <robert.f...@linaro.org>
Cc: Laurent Pinchart <laurent.pinch...@ideasonboard.com>
Cc: Jonas Karlman <jo...@kwiboo.se>
Cc: Jernej Skrabec <jernej.skra...@siol.net>
Cc: David Airlie <airl...@linux.ie>
Cc: Daniel Vetter <dan...@ffwll.ch>
Cc: Guido Günther <a...@sigxcpu.org>
Cc: Robert Chiras <robert.chi...@nxp.com>
Cc: NXP Linux Team <linux-...@nxp.com>
Signed-off-by: Liu Ying <victor....@nxp.com>
---
v2->v3:
* Split from the single patch in v2 to clarify changes. (Neil)
drivers/gpu/drm/bridge/nwl-dsi.c | 7 -------
1 file changed, 7 deletions(-)
diff --git a/drivers/gpu/drm/bridge/nwl-dsi.c b/drivers/gpu/drm/bridge/nwl-dsi.c
index c65ca860712d2..601ccc4a7cdc7 100644
--- a/drivers/gpu/drm/bridge/nwl-dsi.c
+++ b/drivers/gpu/drm/bridge/nwl-dsi.c
@@ -856,13 +856,6 @@ nwl_dsi_bridge_mode_set(struct drm_bridge *bridge,
if (ret < 0)
return;
- /*
- * If hs clock is unchanged, we're all good - all parameters are
- * derived from it atm.
- */
- if (new_cfg.mipi_dphy.hs_clk_rate == dsi->phy_cfg.mipi_dphy.hs_clk_rate)
- return;
-
phy_ref_rate = clk_get_rate(dsi->phy_ref_clk);
DRM_DEV_DEBUG_DRIVER(dev, "PHY at ref rate: %lu\n", phy_ref_rate);
/* Save the new desired phy config */
--
2.25.1
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