Hi Dmitry, Thank you for the patch! Yet something to improve:
[auto build test ERROR on next-20210422] [also build test ERROR on v5.12-rc8] [cannot apply to linus/master v5.12-rc8 v5.12-rc7 v5.12-rc6] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Dmitry-Baryshkov/drm-msm-dpu-simplify-dpu_hw_blk-handling/20210422-211129 base: c457d9676496f5a895509f9c510278beaaffc829 config: arm-defconfig (attached as .config) compiler: arm-linux-gnueabi-gcc (GCC) 9.3.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://github.com/0day-ci/linux/commit/c023ff88d40d423b82b71cd504d787049dcd2046 git remote add linux-review https://github.com/0day-ci/linux git fetch --no-tags linux-review Dmitry-Baryshkov/drm-msm-dpu-simplify-dpu_hw_blk-handling/20210422-211129 git checkout c023ff88d40d423b82b71cd504d787049dcd2046 # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross W=1 ARCH=arm If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <l...@intel.com> All errors (new ones prefixed by >>): drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c: In function 'dpu_encoder_phys_vid_setup_timing_engine': >> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c:287:48: error: 'struct >> dpu_hw_blk' has no member named 'id' 287 | intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->id; | ^~ drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c: In function 'dpu_encoder_phys_vid_enable': drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c:464:72: error: 'struct dpu_hw_blk' has no member named 'id' 464 | ctl->ops.update_pending_flush_merge_3d(ctl, phys_enc->hw_pp->merge_3d->id); | ^~ vim +287 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c 25fdd5933e4c0f Jeykumar Sankaran 2018-06-27 239 25fdd5933e4c0f Jeykumar Sankaran 2018-06-27 240 static void dpu_encoder_phys_vid_setup_timing_engine( 25fdd5933e4c0f Jeykumar Sankaran 2018-06-27 241 struct dpu_encoder_phys *phys_enc) 25fdd5933e4c0f Jeykumar Sankaran 2018-06-27 242 { 25fdd5933e4c0f Jeykumar Sankaran 2018-06-27 243 struct drm_display_mode mode; 25fdd5933e4c0f Jeykumar Sankaran 2018-06-27 244 struct intf_timing_params timing_params = { 0 }; 25fdd5933e4c0f Jeykumar Sankaran 2018-06-27 245 const struct dpu_format *fmt = NULL; 25fdd5933e4c0f Jeykumar Sankaran 2018-06-27 246 u32 fmt_fourcc = DRM_FORMAT_RGB888; 25fdd5933e4c0f Jeykumar Sankaran 2018-06-27 247 unsigned long lock_flags; 25fdd5933e4c0f Jeykumar Sankaran 2018-06-27 248 struct dpu_hw_intf_cfg intf_cfg = { 0 }; 25fdd5933e4c0f Jeykumar Sankaran 2018-06-27 249 5e7d4a8407d37a Drew Davenport 2019-12-06 250 if (!phys_enc->hw_ctl->ops.setup_intf_cfg) { 30801221a73781 Zheng Bin 2020-01-23 251 DPU_ERROR("invalid encoder %d\n", phys_enc != NULL); 25fdd5933e4c0f Jeykumar Sankaran 2018-06-27 252 return; 25fdd5933e4c0f Jeykumar Sankaran 2018-06-27 253 } 25fdd5933e4c0f Jeykumar Sankaran 2018-06-27 254 25fdd5933e4c0f Jeykumar Sankaran 2018-06-27 255 mode = phys_enc->cached_mode; b6057cda8f6cac Jeykumar Sankaran 2019-02-13 256 if (!phys_enc->hw_intf->ops.setup_timing_gen) { 25fdd5933e4c0f Jeykumar Sankaran 2018-06-27 257 DPU_ERROR("timing engine setup is not supported\n"); 25fdd5933e4c0f Jeykumar Sankaran 2018-06-27 258 return; 25fdd5933e4c0f Jeykumar Sankaran 2018-06-27 259 } 25fdd5933e4c0f Jeykumar Sankaran 2018-06-27 260 b6057cda8f6cac Jeykumar Sankaran 2019-02-13 261 DPU_DEBUG_VIDENC(phys_enc, "enabling mode:\n"); 25fdd5933e4c0f Jeykumar Sankaran 2018-06-27 262 drm_mode_debug_printmodeline(&mode); 25fdd5933e4c0f Jeykumar Sankaran 2018-06-27 263 25fdd5933e4c0f Jeykumar Sankaran 2018-06-27 264 if (phys_enc->split_role != ENC_ROLE_SOLO) { 25fdd5933e4c0f Jeykumar Sankaran 2018-06-27 265 mode.hdisplay >>= 1; 25fdd5933e4c0f Jeykumar Sankaran 2018-06-27 266 mode.htotal >>= 1; 25fdd5933e4c0f Jeykumar Sankaran 2018-06-27 267 mode.hsync_start >>= 1; 25fdd5933e4c0f Jeykumar Sankaran 2018-06-27 268 mode.hsync_end >>= 1; 25fdd5933e4c0f Jeykumar Sankaran 2018-06-27 269 b6057cda8f6cac Jeykumar Sankaran 2019-02-13 270 DPU_DEBUG_VIDENC(phys_enc, 25fdd5933e4c0f Jeykumar Sankaran 2018-06-27 271 "split_role %d, halve horizontal %d %d %d %d\n", 25fdd5933e4c0f Jeykumar Sankaran 2018-06-27 272 phys_enc->split_role, 25fdd5933e4c0f Jeykumar Sankaran 2018-06-27 273 mode.hdisplay, mode.htotal, 25fdd5933e4c0f Jeykumar Sankaran 2018-06-27 274 mode.hsync_start, mode.hsync_end); 25fdd5933e4c0f Jeykumar Sankaran 2018-06-27 275 } 25fdd5933e4c0f Jeykumar Sankaran 2018-06-27 276 b6057cda8f6cac Jeykumar Sankaran 2019-02-13 277 drm_mode_to_intf_timing_params(phys_enc, &mode, &timing_params); 25fdd5933e4c0f Jeykumar Sankaran 2018-06-27 278 25fdd5933e4c0f Jeykumar Sankaran 2018-06-27 279 fmt = dpu_get_dpu_format(fmt_fourcc); b6057cda8f6cac Jeykumar Sankaran 2019-02-13 280 DPU_DEBUG_VIDENC(phys_enc, "fmt_fourcc 0x%X\n", fmt_fourcc); 25fdd5933e4c0f Jeykumar Sankaran 2018-06-27 281 b6057cda8f6cac Jeykumar Sankaran 2019-02-13 282 intf_cfg.intf = phys_enc->hw_intf->idx; 25fdd5933e4c0f Jeykumar Sankaran 2018-06-27 283 intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_VID; 25fdd5933e4c0f Jeykumar Sankaran 2018-06-27 284 intf_cfg.stream_sel = 0; /* Don't care value for video mode */ 25fdd5933e4c0f Jeykumar Sankaran 2018-06-27 285 intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc); 3e79527a33a83b Dmitry Baryshkov 2020-10-22 286 if (phys_enc->hw_pp->merge_3d) 3e79527a33a83b Dmitry Baryshkov 2020-10-22 @287 intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->id; 25fdd5933e4c0f Jeykumar Sankaran 2018-06-27 288 25fdd5933e4c0f Jeykumar Sankaran 2018-06-27 289 spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags); b6057cda8f6cac Jeykumar Sankaran 2019-02-13 290 phys_enc->hw_intf->ops.setup_timing_gen(phys_enc->hw_intf, 25fdd5933e4c0f Jeykumar Sankaran 2018-06-27 291 &timing_params, fmt); 25fdd5933e4c0f Jeykumar Sankaran 2018-06-27 292 phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg); 73bfb790ac786c Kalyan Thota 2019-11-25 293 73bfb790ac786c Kalyan Thota 2019-11-25 294 /* setup which pp blk will connect to this intf */ 73bfb790ac786c Kalyan Thota 2019-11-25 295 if (phys_enc->hw_intf->ops.bind_pingpong_blk) 73bfb790ac786c Kalyan Thota 2019-11-25 296 phys_enc->hw_intf->ops.bind_pingpong_blk( 73bfb790ac786c Kalyan Thota 2019-11-25 297 phys_enc->hw_intf, 73bfb790ac786c Kalyan Thota 2019-11-25 298 true, 73bfb790ac786c Kalyan Thota 2019-11-25 299 phys_enc->hw_pp->idx); 73bfb790ac786c Kalyan Thota 2019-11-25 300 3e79527a33a83b Dmitry Baryshkov 2020-10-22 301 if (phys_enc->hw_pp->merge_3d) { 3e79527a33a83b Dmitry Baryshkov 2020-10-22 302 struct dpu_hw_merge_3d *merge_3d = to_dpu_hw_merge_3d(phys_enc->hw_pp->merge_3d); 3e79527a33a83b Dmitry Baryshkov 2020-10-22 303 3e79527a33a83b Dmitry Baryshkov 2020-10-22 304 merge_3d->ops.setup_3d_mode(merge_3d, intf_cfg.mode_3d); 3e79527a33a83b Dmitry Baryshkov 2020-10-22 305 } 3e79527a33a83b Dmitry Baryshkov 2020-10-22 306 25fdd5933e4c0f Jeykumar Sankaran 2018-06-27 307 spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags); 25fdd5933e4c0f Jeykumar Sankaran 2018-06-27 308 25fdd5933e4c0f Jeykumar Sankaran 2018-06-27 309 programmable_fetch_config(phys_enc, &timing_params); 25fdd5933e4c0f Jeykumar Sankaran 2018-06-27 310 } 25fdd5933e4c0f Jeykumar Sankaran 2018-06-27 311 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org
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