The value programmed into horizontal porch and sync registers must be
scaled to the correct number of DSI lanes and bpp, make it so.

Signed-off-by: Marek Vasut <ma...@denx.de>
Cc: Fabio Estevam <feste...@gmail.com>
Cc: Guido Günther <a...@sigxcpu.org>
Cc: Jaehoon Chung <jh80.ch...@samsung.com>
Cc: Lucas Stach <l.st...@pengutronix.de>
Cc: Marek Szyprowski <m.szyprow...@samsung.com>
Cc: Michael Tretter <m.tret...@pengutronix.de>
Cc: NXP Linux Team <linux-...@nxp.com>
Cc: Shawn Guo <shawn...@kernel.org>
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-samsung-...@vger.kernel.org
To: dri-devel@lists.freedesktop.org
--
NOTE: This depends on 
https://patchwork.kernel.org/project/dri-devel/list/?series=347439
---
 drivers/gpu/drm/bridge/samsung-dsim.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c 
b/drivers/gpu/drm/bridge/samsung-dsim.c
index fbd87a74eb9f..42b49546dd00 100644
--- a/drivers/gpu/drm/bridge/samsung-dsim.c
+++ b/drivers/gpu/drm/bridge/samsung-dsim.c
@@ -740,20 +740,23 @@ static void samsung_dsim_set_display_mode(struct 
samsung_dsim *dsi)
 {
        struct drm_display_mode *m = &dsi->mode;
        unsigned int num_bits_resol = dsi->driver_data->num_bits_resol;
+       int bpp;
        u32 reg;
 
        if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
+               bpp = mipi_dsi_pixel_format_to_bpp(dsi->format) / 8;
+
                reg = DSIM_CMD_ALLOW(0xf)
                        | DSIM_STABLE_VFP(m->vsync_start - m->vdisplay)
                        | DSIM_MAIN_VBP(m->vtotal - m->vsync_end);
                samsung_dsim_write(dsi, DSIM_MVPORCH_REG, reg);
 
-               reg = DSIM_MAIN_HFP(m->hsync_start - m->hdisplay)
-                       | DSIM_MAIN_HBP(m->htotal - m->hsync_end);
+               reg = DSIM_MAIN_HFP((m->hsync_start - m->hdisplay) * bpp / 
dsi->lanes)
+                       | DSIM_MAIN_HBP((m->htotal - m->hsync_end) * bpp / 
dsi->lanes);
                samsung_dsim_write(dsi, DSIM_MHPORCH_REG, reg);
 
                reg = DSIM_MAIN_VSA(m->vsync_end - m->vsync_start)
-                       | DSIM_MAIN_HSA(m->hsync_end - m->hsync_start);
+                       | DSIM_MAIN_HSA((m->hsync_end - m->hsync_start) * bpp / 
dsi->lanes);
                samsung_dsim_write(dsi, DSIM_MSYNC_REG, reg);
        }
        reg =  DSIM_MAIN_HRESOL(m->hdisplay, num_bits_resol) |
-- 
2.28.0

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

Reply via email to