Starting from the JZ4725B SoC, the primary and overlay planes support
24-bit pixel modes (8 bits per color component, without dummy byte).
Add support for these in the ingenic-drm driver.
Signed-off-by: Paul Cercueil <p...@crapouillou.net>
---
drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 8 ++++++++
drivers/gpu/drm/ingenic/ingenic-drm.h | 2 ++
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
index 9e3122b42820..c2b63533ed18 100644
--- a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
+++ b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c
@@ -458,6 +458,9 @@ void ingenic_drm_plane_config(struct device *dev,
case DRM_FORMAT_RGB565:
ctrl |= JZ_LCD_OSDCTRL_BPP_15_16;
break;
+ case DRM_FORMAT_RGB888:
+ ctrl |= JZ_LCD_OSDCTRL_BPP_24_COMP;
+ break;
case DRM_FORMAT_XRGB8888:
ctrl |= JZ_LCD_OSDCTRL_BPP_18_24;
break;
@@ -479,6 +482,9 @@ void ingenic_drm_plane_config(struct device *dev,
case DRM_FORMAT_RGB565:
ctrl |= JZ_LCD_CTRL_BPP_15_16;
break;
+ case DRM_FORMAT_RGB888:
+ ctrl |= JZ_LCD_CTRL_BPP_24_COMP;
+ break;
case DRM_FORMAT_XRGB8888:
ctrl |= JZ_LCD_CTRL_BPP_18_24;
break;
@@ -1278,6 +1284,7 @@ static const u32 jz4725b_formats_f0[] = {
static const u32 jz4770_formats_f1[] = {
DRM_FORMAT_XRGB1555,
DRM_FORMAT_RGB565,
+ DRM_FORMAT_RGB888,
DRM_FORMAT_XRGB8888,
DRM_FORMAT_XRGB2101010,
};
@@ -1286,6 +1293,7 @@ static const u32 jz4770_formats_f0[] = {
DRM_FORMAT_C8,
DRM_FORMAT_XRGB1555,
DRM_FORMAT_RGB565,
+ DRM_FORMAT_RGB888,
DRM_FORMAT_XRGB8888,
DRM_FORMAT_XRGB2101010,
};
diff --git a/drivers/gpu/drm/ingenic/ingenic-drm.h
b/drivers/gpu/drm/ingenic/ingenic-drm.h
index f05e18e6b6fa..ee3a892c0383 100644
--- a/drivers/gpu/drm/ingenic/ingenic-drm.h
+++ b/drivers/gpu/drm/ingenic/ingenic-drm.h
@@ -124,6 +124,7 @@
#define JZ_LCD_CTRL_BPP_8 0x3
#define JZ_LCD_CTRL_BPP_15_16 0x4
#define JZ_LCD_CTRL_BPP_18_24 0x5
+#define JZ_LCD_CTRL_BPP_24_COMP 0x6
#define JZ_LCD_CTRL_BPP_30 0x7
#define JZ_LCD_CTRL_BPP_MASK (JZ_LCD_CTRL_RGB555 | 0x7)
@@ -146,6 +147,7 @@
#define JZ_LCD_OSDCTRL_CHANGE BIT(3)
#define JZ_LCD_OSDCTRL_BPP_15_16 0x4
#define JZ_LCD_OSDCTRL_BPP_18_24 0x5
+#define JZ_LCD_OSDCTRL_BPP_24_COMP 0x6
#define JZ_LCD_OSDCTRL_BPP_30 0x7
#define JZ_LCD_OSDCTRL_BPP_MASK (JZ_LCD_OSDCTRL_RGB555
| 0x7)
--
2.28.0
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