Hi Tomi,
Thank you for the patch.
On Wed, Sep 23, 2020 at 11:30:57AM +0300, Tomi Valkeinen wrote:
> On x64 we get:
>
> drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c:751:10: warning:
> conversion from 'long unsigned int' to 'unsigned int' changes value from
> '18446744073709551613' to '4294967293' [-Woverflow]
>
> The registers are 32 bit, so fix by casting to u32.
I wonder if we need a BIT32 macro... This is a common issue, it would be
nice to handle it in the macros that define register fields.
> Fixes: fb43aa0acdfd ("drm: bridge: Add support for Cadence MHDP8546 DPI/DP
> bridge")
> Signed-off-by: Tomi Valkeinen <tomi.valkei...@ti.com>
> ---
> drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
> b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
> index 621ebdbff8a3..d0c65610ebb5 100644
> --- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
> +++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
> @@ -748,7 +748,7 @@ static int cdns_mhdp_fw_activate(const struct firmware
> *fw,
> * bridge should already be detached.
> */
> if (mhdp->bridge_attached)
> - writel(~CDNS_APB_INT_MASK_SW_EVENT_INT,
> + writel(~(u32)CDNS_APB_INT_MASK_SW_EVENT_INT,
> mhdp->regs + CDNS_APB_INT_MASK);
>
> spin_unlock(&mhdp->start_lock);
> @@ -1689,7 +1689,7 @@ static int cdns_mhdp_attach(struct drm_bridge *bridge,
>
> /* Enable SW event interrupts */
> if (hw_ready)
> - writel(~CDNS_APB_INT_MASK_SW_EVENT_INT,
> + writel(~(u32)CDNS_APB_INT_MASK_SW_EVENT_INT,
> mhdp->regs + CDNS_APB_INT_MASK);
>
> return 0;
> @@ -2122,7 +2122,7 @@ static void cdns_mhdp_bridge_hpd_enable(struct
> drm_bridge *bridge)
>
> /* Enable SW event interrupts */
> if (mhdp->bridge_attached)
> - writel(~CDNS_APB_INT_MASK_SW_EVENT_INT,
> + writel(~(u32)CDNS_APB_INT_MASK_SW_EVENT_INT,
> mhdp->regs + CDNS_APB_INT_MASK);
> }
>
--
Regards,
Laurent Pinchart
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