From: Alex Deucher <alexander.deuc...@amd.com> CP changes: - make sure the new VM base address hits the registers - wait for the VM invalidate to finish DMA changes: - wait for the VM invalidate to finish
May fix: https://bugs.freedesktop.org/show_bug.cgi?id=58354 https://bugs.freedesktop.org/show_bug.cgi?id=58667 possibly other related issues. Signed-off-by: Alex Deucher <alexander.deuc...@amd.com> --- drivers/gpu/drm/radeon/ni.c | 32 ++++++++++++++++++++++++++++++-- drivers/gpu/drm/radeon/nid.h | 5 +++++ 2 files changed, 35 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c index 39e8be1..2b10ab6 100644 --- a/drivers/gpu/drm/radeon/ni.c +++ b/drivers/gpu/drm/radeon/ni.c @@ -1861,12 +1861,25 @@ void cayman_vm_set_page(struct radeon_device *rdev, uint64_t pe, void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm) { struct radeon_ring *ring = &rdev->ring[ridx]; + u32 vm_reg, vm_addr; if (vm == NULL) return; - radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2), 0)); - radeon_ring_write(ring, vm->pd_gpu_addr >> 12); + vm_reg = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2); + vm_addr = vm->pd_gpu_addr >> 12; + + radeon_ring_write(ring, PACKET0(vm_reg, 0)); + radeon_ring_write(ring, vm_addr); + + /* wait for the new value to hit the reg */ + radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); + radeon_ring_write(ring, 3); /* == */ + radeon_ring_write(ring, vm_reg >> 2); + radeon_ring_write(ring, 0); + radeon_ring_write(ring, vm_addr); /* ref */ + radeon_ring_write(ring, 0xfffffff); /* mask */ + radeon_ring_write(ring, 0x10); /* flush hdp cache */ radeon_ring_write(ring, PACKET0(HDP_MEM_COHERENCY_FLUSH_CNTL, 0)); @@ -1876,6 +1889,15 @@ void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm) radeon_ring_write(ring, PACKET0(VM_INVALIDATE_REQUEST, 0)); radeon_ring_write(ring, 1 << vm->id); + /* wait for the request bit to clear */ + radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); + radeon_ring_write(ring, 3); /* == */ + radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); + radeon_ring_write(ring, 0); + radeon_ring_write(ring, 0); /* ref */ + radeon_ring_write(ring, 1 << vm->id); /* mask */ + radeon_ring_write(ring, 0x10); + /* sync PFP to ME, otherwise we might get invalid PFP reads */ radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); radeon_ring_write(ring, 0x0); @@ -1901,5 +1923,11 @@ void cayman_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0)); radeon_ring_write(ring, (0xf << 16) | (VM_INVALIDATE_REQUEST >> 2)); radeon_ring_write(ring, 1 << vm->id); + + /* wait for the request bit to clear */ + radeon_ring_write(ring, DMA_SRBM_READ_PACKET(DMA_PACKET_SRBM_WRITE, 1, 0)); + radeon_ring_write(ring, (0xfff << 20) | (VM_INVALIDATE_REQUEST >> 2)); + radeon_ring_write(ring, 1 << vm->id); /* mask */ + radeon_ring_write(ring, 0); /* value */ } diff --git a/drivers/gpu/drm/radeon/nid.h b/drivers/gpu/drm/radeon/nid.h index b93186b..f2e73e7 100644 --- a/drivers/gpu/drm/radeon/nid.h +++ b/drivers/gpu/drm/radeon/nid.h @@ -663,6 +663,11 @@ (((vmid) & 0xF) << 20) | \ (((n) & 0xFFFFF) << 0)) +#define DMA_SRBM_READ_PACKET(cmd, p, n) ((((cmd) & 0xF) << 28) | \ + (1 << 27) | \ + (((p) & 0x1) << 26) | \ + (((n) & 0xFFFFF) << 0)) + /* async DMA Packet types */ #define DMA_PACKET_WRITE 0x2 #define DMA_PACKET_COPY 0x3 -- 1.7.7.5 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel
